Robert B. Reese

According to our database, Robert B. Reese authored at least 18 papers between 1993 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2015

CE2016 steering committee: a short update.

Susan Conry, Eric Durant, Herman Lam, Victor P. Nelson, Robert B. Reese

Inroads, 2015

CE2016: Updated computer engineering curriculum guidelines.

Eric Durant, John Impagliazzo, Susan Conry, Robert B. Reese, Herman Lam, Victor P. Nelson, Joseph L. Hughes, Weidong Liu, Junlin Lu, Andrew D. McGettrick

Proceedings of the 2015 IEEE Frontiers in Education Conference, 2015

2014

Setting the stage for CE2016: A revised body of knowledge.

Eric Durant, John Impagliazzo, Susan Conry, Robert B. Reese, Mitchell A. Thornton, Herman Lam, Victor P. Nelson

Proceedings of the IEEE Frontiers in Education Conference, 2014

2012

Uncle - An RTL Approach to Asynchronous Design.

Robert B. Reese, Scott C. Smith, Mitchell A. Thornton

Proceedings of the 18th IEEE International Symposium on Asynchronous Circuits and Systems, 2012

2007

Finite State Machine Datapath Design, Optimization, and Implementation

Justin Davis, Robert B. Reese

Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79776-7, 2007

2006

Introduction to Logic Synthesis using Verilog HDL

Robert B. Reese, Mitchell A. Thornton

Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool Publishers, ISBN: 978-3-031-79743-9, 2006

2005

Early evaluation for performance enhancement in phased logic.

Robert B. Reese, Mitchell A. Thornton, Cherrice Traver, David Hemmendinger

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

A Coarse-Grain Phased Logic CPU.

Robert B. Reese, Mitchell A. Thornton, Cherrice Traver

IEEE Trans. Computers, 2005

2004

Cooperative and progressive design experience for embedded systems.

Jerry W. Bruce, James C. Harden, Robert B. Reese

IEEE Trans. Educ., 2004

Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion.

Kenneth Fazel, Lun Li, Mitchell A. Thornton, Robert B. Reese, Cherrice Traver

Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

2003

A Fine-Grain Phased Logic CPU.

Robert B. Reese, Mitchell A. Thornton, Cherrice Traver

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

PLFire: A Visualization Tool for Asynchronous Phased Logic Designs.

Kenneth Fazel, Mitchell A. Thornton, Robert B. Reese

Proceedings of the 2003 Design, 2003

2002

Generalized Early Evaluation in Self-Timed Circuits.

Mitchell A. Thornton, Kenneth Fazel, Robert B. Reese, Cherrice Traver

Proceedings of the 2002 Design, 2002

2001

Arithmetic Logic Circuits Using Self-Timed Bit Level Dataflow and Early Evaluation.

Robert B. Reese, Mitchell A. Thornton, Cherrice Traver

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

2000

OpenDesign: An Open User-Configurable Project Environment for Collaborative Design and Execution on the Internet.

Hemang Lavana, Franc Brglez, Robert B. Reese, Gangadhar Konduri, Anantha P. Chandrakasan

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1999

User-configurable experimental design flows on the web: the ISCAS'99 experiments.

Hemang Lavana, Franc Brglez, Robert B. Reese

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1997

Developing and Distributing Component-Level VHDL Models.

J. Scott Calhoun, Vijay K. Madisetti, Robert B. Reese, Thomas Egolf

J. VLSI Signal Process., 1997

1993

A Comparison of Synchronous and Asynchronous FSMD Designs.

Richard Auletta, Robert B. Reese, Cherrice Traver

Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993