Rob A. Rutenbar

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Hardware Architecture of a Number Theoretic Transform for a Bootstrappable RNS-based Homomorphic Encryption Scheme.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

2019

FPGA-based Accelerators of Fully Pipelined Modular Multipliers for Homomorphic Encryption.

[BibT_eX]

[DOI]

Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

An Area-Efficient Iterative Single-Precision Floating-Point Multiplier Architecture for FPGA.

[BibT_eX]

[DOI]

Sunwoong Kim

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Accelerating Bayesian Inference on Structured Graphs Using Parallel Gibbs Sampling.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

A Pixel-Parallel Virtual-Image Architecture for High Performance and Power Efficient Graph Cuts Inference.

[BibT_eX]

[DOI]

Tianqi Gao

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

FlexGibbs: Reconfigurable Parallel Gibbs Sampling Accelerator for Structured Graphs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

A Virtual Image Accelerator for Graph Cuts Inference on FPGA.

[BibT_eX]

[DOI]

Tianqi Gao

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

Real-Time and Low-Power Streaming Source Separation Using Markov Random Field.

[BibT_eX]

[DOI]

Glenn G. Ko

ACM J. Emerg. Technol. Comput. Syst., 2018

Realizing the potential of data science.

[BibT_eX]

[DOI]

Francine Berman

Brent Hailpern

Henrik I. Christensen

Commun. ACM, 2018

Accelerator Design with Effective Resource Utilization for Binary Convolutional Neural Networks on an FPGA.

[BibT_eX]

[DOI]

Sunwoong Kim

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

2017

A case study of machine learning hardware: Real-time source separation using Markov Random Fields via sampling-based inference.

[BibT_eX]

[DOI]

Glenn G. Ko

Proceedings of the 2017 IEEE International Conference on Acoustics, 2017

Toward a pixel-parallel architecture for graph cuts inference on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016

Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2016

Video-Rate Stereo Matching Using Markov Random Field TRW-S Inference on a Hybrid CPU+FPGA Computing Platform.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2016

Keynote address Wednesday: Hardware inference accelerators for machine learning.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Analysis of error resiliency of belief propagation in computer vision.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Acoustics, 2016

Configurable and scalable belief propagation accelerator for computer vision.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

2015

Analog Circuit and Layout Synthesis Revisited.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

Fast hierarchical implementation of sequential tree-reweighted belief propagation for probabilistic inference.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014

DAC at 50: The Second 25 Years.

[BibT_eX]

[DOI]

IEEE Des. Test, 2014

A robust message passing based stereo matching kernel via system-level error resiliency.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2014

The First EDA MOOC: Teaching Design Automation to Planet Earth.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Efficiently Enforcing Diversity in Multi-Output Structured Prediction.

[BibT_eX]

[DOI]

Proceedings of the Seventeenth International Conference on Artificial Intelligence and Statistics, 2014

2013

Efficient Spatial Pattern Analysis for Variation Decomposition Via Robust Sparse Regression.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Error resilient MRF message passing architecture for stereo matching.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

FPGA acceleration of Markov Random Field TRW-S inference for stereo matching.

[BibT_eX]

[DOI]

Proceedings of the 11th ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2013

EMERALD: Characterization of emerging applications and algorithms for low-power devices.

[BibT_eX]

[DOI]

Vijaykrishnan Narayanan

Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Automatic clustering of wafer spatial signatures.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

Stereophonic spectrogram segmentation using Markov random fields.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Workshop on Machine Learning for Signal Processing, 2012

Spatial variation decomposition via sparse regression.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on IC Design & Technology, 2012

Hardware implementation of MRF map inference on an FPGA platform.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers.

[BibT_eX]

[DOI]

Jeffrey R. Johnston

Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011

Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Toward efficient spatial variation decomposition via sparse regression.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010

Two Fast Methods for Estimating the Minimum Standby Supply Voltage for Large SRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Why Quasi-Monte Carlo is Better Than Monte Carlo or Latin Hypercube Sampling for Statistical Circuit Analysis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Analog layout synthesis: what's missing?

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Physical Design, 2010

Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Bayesian virtual probe: minimizing variation characterization cost for nanoscale IC technologies via Bayesian inference.

[BibT_eX]

[DOI]

Wangyang Zhang

Xin Li

Proceedings of the 47th Design Automation Conference, 2010

2009

Novel Algorithms for Fast Statistical Analysis of Scaled Circuits

[BibT_eX]

[DOI]

Lecture Notes in Electrical Engineering 46, Springer, ISBN: 978-90-481-3099-3, 2009

Statistical Blockade: Very Fast Statistical Simulation and Modeling of Rare Circuit Events and Its Application to Memory Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Profiling large-vocabulary continuous speech recognition on embedded devices: a hardware resource sensitivity analysis.

[BibT_eX]

[DOI]

Kai Yu

Proceedings of the 10th Annual Conference of the International Speech Communication Association, 2009

Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits.

[BibT_eX]

[DOI]

Xin Li

R. D. (Shawn) Blanton

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

A multi-fpga 10x-real-time high-speed search engine for a 5000-word vocabulary speech recognizer.

[BibT_eX]

[DOI]

Edward C. Lin

Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, 2009

Oil fields, hedge funds, and drugs.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

2008

Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Digital Circuit Design Challenges and Opportunities in the Era of Nanoscale CMOS.

[BibT_eX]

[DOI]

Proc. IEEE, 2008

Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

A low-power hardware search architecture for speech recognition.

[BibT_eX]

[DOI]

Patrick J. Bourke

Proceedings of the 9th Annual Conference of the International Speech Communication Association, 2008

Practical, fast Monte Carlo statistical static timing analysis: why and how.

[BibT_eX]

[DOI]

Sonia Singhal

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Exploiting Correlation Kernels for Efficient Handling of Intra-Die Spatial Correlation, with Application to Statistical Timing.

[BibT_eX]

[DOI]

Sonia Singhal

Proceedings of the Design, Automation and Test in Europe, 2008

Verifying really complex systems: on earth and beyond.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

Interval-Valued Reduced-Order Statistical Interconnect Modeling.

[BibT_eX]

[DOI]

James D. Ma

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Hierarchical Modeling, Optimization, and Synthesis for System-Level Analog and RF Designs.

[BibT_eX]

[DOI]

Georges G. E. Gielen

Jaijeet S. Roychowdhury

Proc. IEEE, 2007

Collaborative VLSI-CAD Instruction in the Digital Sandbox.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

From Finance to Flip Flops: A Study of Fast Quasi-Monte Carlo Methods from Computational Finance Applied to Statistical Circuit Analysis.

[BibT_eX]

[DOI]

Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Mixed-size placement with fixed macrocells using grid-warping.

[BibT_eX]

[DOI]

Zhong Xiu

Proceedings of the 2007 International Symposium on Physical Design, 2007

Generating small, accurate acoustic models with a modified Bayesian information criterion.

[BibT_eX]

[DOI]

Kai Yu

Proceedings of the 8th Annual Conference of the International Speech Communication Association, 2007

A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 15th International Symposium on Field Programmable Gate Arrays, 2007

Statistical modeling for the minimum standby supply voltage of a full SRAM array.

[BibT_eX]

[DOI]

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

Statistical blockade: a novel method for very fast Monte Carlo simulation of rare circuit events, and its application.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Beyond Low-Order Statistical Response Surfaces: Latent Variable Regression for Efficient, Highly Nonlinear Fitting.

[BibT_eX]

[DOI]

Proceedings of the 44th Design Automation Conference, 2007

Next-Generation Design and EDA Challenges: Small Physics, Big Systems, and Tall Tool-Chains.

[BibT_eX]

[DOI]

Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006

Fast Interval-Valued Statistical Modeling of Interconnect and Effective Capacitance.

[BibT_eX]

[DOI]

James D. Ma

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Moving speech recognition from software to silicon: the in silico vox project.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Conference on Spoken Language Processing, 2006

Faster, parametric trajectory-based macromodels via localized linear reductions.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Design automation for analog: the next generation of tool challenges.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

In silico vox: Towards speech recognition in silicon.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE Hot Chips 18 Symposium (HCS), 2006

Verifying analog oscillator circuits using forward/backward abstraction refinement.

[BibT_eX]

[DOI]

Goran Frehse

Bruce H. Krogh

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration.

[BibT_eX]

[DOI]

Pragati K. Tiwary

Proceedings of the 43rd Design Automation Conference, 2006

On-the-Fly Fidelity Assessment for Trajectory-Based Circuit Macromodels.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

2005

Time Domain Verification of Oscillator Circuit Properties.

[BibT_eX]

[DOI]

Proceedings of the First Workshop on Formal Verification of Analog Circuits, 2005

Early research experience with OpenAccess gear: an open source development environment for physical design.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Symposium on Physical Design, 2005

Fast interval-valued statistical interconnect modeling and reduction.

[BibT_eX]

[DOI]

James D. Z. Ma

Proceedings of the 2005 International Symposium on Physical Design, 2005

Interval-valued statistical modeling of oxide chemical-mechanical polishing.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Timing-driven placement by grid-warping.

[BibT_eX]

[DOI]

Zhong Xiu

Proceedings of the 42nd Design Automation Conference, 2005

Scalable trajectory methods for on-demand analog macromodel extraction.

[BibT_eX]

[DOI]

Proceedings of the 42nd Design Automation Conference, 2005

2004

A Comparative Study of Two Boolean Formulations of FPGA Detailed Routing Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2004

Static statistical timing analysis for latch-based pipeline designs.

[BibT_eX]

[DOI]

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Towards formal verification of analog designs.

[BibT_eX]

[DOI]

Smriti Gupta

Bruce H. Krogh

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Large-scale placement by grid-warping.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Will Moore's Law rule in the land of analog?

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

2003

sub-SAT: a formulation for relaxed Boolean satisfiability with applications in routing.

[BibT_eX]

[DOI]

Hui Xu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Fast, Accurate Static Analysis for Fixed-Point Finite-Precision Effects in DSP Designs.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Floating-point error analysis based on affine arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Acoustics, 2003

Mixed signals on mixed-signal: the right next technology.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

Toward efficient static analysis of finite-precision effects in DSP applications via affine arithmetic modeling.

[BibT_eX]

[DOI]

Proceedings of the 40th Design Automation Conference, 2003

2002

A new FPGA detailed routing approach via search-based Booleansatisfiability.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Lightweight Floating-Point Arithmetic: Case Study of Inverse Discrete Cosine Transform.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2002

Floating-point bit-width optimization for low-power signal processing applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2002

Hybrid Routing for FPGAs by Integrating Boolean Satisfiability with Geometric Search.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

Remembrance of circuits past: macromodeling by data mining in large analog design spaces.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

2001

Wire packing - a strong formulation of crosstalk-aware chip-leveltrack/layer assignment with an efficient integer programming solution.

[BibT_eX]

[DOI]

Rony Kay

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Low-power technology mapping for mixed-swing logic.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Automatic Hierarchical Design: Fantasy or Reality? (Panel).

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Embedded Tutorial: CAD Solutions and Outstanding Challenges for Mixed-Signal and RF IC Design.

[BibT_eX]

[DOI]

Domine Leenaerts

Georges G. E. Gielen

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Direct Transistor-Level Layout for Digital Blocks.

[BibT_eX]

[DOI]

Prakash Gopalakrishnan

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Synthesis for Industrial-Scale Analog Intellectual Property.

[BibT_eX]

[DOI]

Proceedings of the 3rd NASA / DoD Workshop on Evolvable Hardware (EH 2001), 2001

A boolean satisfiability-based incremental rerouting approach with application to FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Panel: (When) Will FPGAs Kill ASICs?

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Reducing power by optimizing the necessary precision/range of floating-point arithmetic.

[BibT_eX]

[DOI]

J. Y. F. Tong

David Nagle

IEEE Trans. Very Large Scale Integr. Syst., 2000

Anaconda: simulation-based synthesis of analog circuits viastochastic pattern search.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Efficient handling of operating range and manufacturing linevariations in analog cell synthesis.

[BibT_eX]

[DOI]

Tamal Mukherjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Computer-aided design of analog and mixed-signal integrated circuits.

[BibT_eX]

[DOI]

Georges G. E. Gielen

Proc. IEEE, 2000

Layout tools for analog ICs and mixed-signal SoCs: a survey.

[BibT_eX]

[DOI]

John M. Cohn

Proceedings of the 2000 International Symposium on Physical Design, 2000

Wire packing: a strong formulation of crosstalk-aware chip-level track/layer assignment with an efficient integer programming solution.

[BibT_eX]

[DOI]

Rony Kay

Proceedings of the 2000 International Symposium on Physical Design, 2000

Life at the end of CMOS scaling (and beyond) (panel session) (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

A case study of synthesis for industrial-scale analog IP: redesign of the equalizer/filter frontend for an ADSL CODEC.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Survival strategies for mixed-signal systems-on-chip (panel session).

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Case studies: Chip design on the bleeding edge (panel session abstract).

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

1999

Device-level early floorplanning algorithms for RF circuits.

[BibT_eX]

[DOI]

Mehmet Aktuna

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Satisfiability-Based Detailed FPGA Routing.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Inverse polarity techniques for high-speed/low-power multipliers.

[BibT_eX]

[DOI]

Pascal C. H. Meier

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Satisfiability-Based Layout Revisited: Detailed Routing of Complex FPGAs vis Search-Based Boolean SAT.

[BibT_eX]

[DOI]

Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999

MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

ANACONDA: robust synthesis of analog circuits via stochastic pattern search.

[BibT_eX]

[DOI]

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

FPGA routing and routability estimation via Boolean satisfiability.

[BibT_eX]

[DOI]

R. Glenn Wood

IEEE Trans. Very Large Scale Integr. Syst., 1998

Performance-driven simultaneous placement and routing for FPGA's.

[BibT_eX]

[DOI]

Sudip Nag

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

1997

A hierarchical decomposition methodology for multistage clock circuits.

[BibT_eX]

[DOI]

Gary Ellis

Lawrence T. Pileggi

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

1996

Synthesis of high-performance analog circuits in ASTRX/OBLX.

[BibT_eX]

[DOI]

Emil S. Ochotta

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Synthesis Tools for Mixed-Signal ICs: Progress on Frontend and Backend Strategies.

[BibT_eX]

[DOI]

Proceedings of the 33st Conference on Design Automation, 1996

An <i>O(n)</i> Algorithm for Transistor Stacking with Performance Constraints.

[BibT_eX]

[DOI]

Bülent Basaran

Proceedings of the 33st Conference on Design Automation, 1996

1995

Addressing noise decoupling in mixed-signal IC's: power distribution design and cell customization.

[BibT_eX]

[DOI]

Balsha R. Stanisic

IEEE J. Solid State Circuits, March, 1995

Substrate-aware mixed-signal macrocell placement in WRIGHT.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, March, 1995

Integer programming based topology selection of cell-level analog circuits.

[BibT_eX]

[DOI]

Prabir C. Maulik

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Reengineering the curriculum: design and analysis of a new undergraduate Electrical and Computer Engineering degree at Carnegie Mellon University.

[BibT_eX]

[DOI]

Proc. IEEE, 1995

Testability-oriented channel routing.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Performance-driven simultaneous place and route for island-style FPGAs.

[BibT_eX]

[DOI]

Sudip K. Nag

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

1994

Addressing substrate coupling in mixed-mode ICs: simulation and power distribution synthesis.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, March, 1994

Synthesis of manufacturable analog circuits.

[BibT_eX]

[DOI]

Tamal Mukherjee

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

ASTRX/OBLX: Tools for Rapid Synthesis of High-Performance Analog Circuits.

[BibT_eX]

[DOI]

Emil S. Ochotta

Proceedings of the 31st Conference on Design Automation, 1994

Performance-Driven Simultaneous Place and Route for Row-Based FPGAs.

[BibT_eX]

[DOI]

Sudip Nag

Proceedings of the 31st Conference on Design Automation, 1994

1993

Latchup-aware placement and parasitic-bounded routing of custom analog cells.

[BibT_eX]

[DOI]

Bülent Basaran

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992

Knowledge Representation and Reasoning in a Software Synthesis Architecture.

[BibT_eX]

[DOI]

Dorothy E. Setliff

IEEE Trans. Software Eng., 1992

System-level routing of mixed-signal ASICs in WREN.

[BibT_eX]

[DOI]

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

A Mixed-Integer Nonlinear Programming Approach to Analog Circuit Synthesis.

[BibT_eX]

[DOI]

Prabir C. Maulik

Proceedings of the 29th Design Automation Conference, 1992

1991

On the feasibility of synthesizing CAD software from specifications: generating maze router tools in ELF.

[BibT_eX]

[DOI]

Dorothy E. Setliff

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Massively parallel switch-level simulation: a feasibility study.

[BibT_eX]

[DOI]

Randal E. Bryant

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

A Parallel Steiner Heuristic for Wirelength Estimation of Large Net Populations.

[BibT_eX]

[DOI]

Rajeev Jayaraman

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

Techniques for Simultaneous Placement and Routing of Custom Analog Cells in KOAN/ANAGRAM II.

[BibT_eX]

[DOI]

Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990

Design and Performance Evaluation of New Massively Parallel VLSI Mask Verification Algorithms in JIGSAW.

[BibT_eX]

[DOI]

Erik C. Carlson

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

OASYS: a framework for analog circuit synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Logic Simulation on Massively Parallel Architectures.

[BibT_eX]

[DOI]

Randal E. Bryant

Proceedings of the 16th Annual International Symposium on Computer Architecture. Jerusalem, 1989

Zen and the Art of Analog Design Automation.

[BibT_eX]

Proceedings of the Information Processing 89, Proceedings of the IFIP 11th World Computer Congress, San Francisco, USA, August 28, 1989

ELF: A Tool for Automatic Synthesis of Custom Physical CAD Software.

[BibT_eX]

[DOI]

Dorothy E. Setliff

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1988

Systolic routing hardware: performance evaluation and optimization.

[BibT_eX]

[DOI]

Daniel E. Atkins

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Analog circuit synthesis and exploration in OASYS.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Analog circuit synthesis for performance in OASYS.

[BibT_eX]

[DOI]

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Automatic layout of custom analog cells in ANAGRAM.

[BibT_eX]

[DOI]

David J. Garrod

Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988

Mask Verification on the Connection Machine.

[BibT_eX]

[DOI]

Erik C. Carlson

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Placement by Simulated Annealing on a Multiprocessor.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A Scanline Data Structure Processor for VLSI Geometry Checking.

[BibT_eX]

[DOI]

Erik C. Carlson

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

A Prototype Framework for Knowledge-Based Analog Circuit Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28, 1987

1986

Multiprocessor-based placement by simulated annealing.

[BibT_eX]

[DOI]

Proceedings of the 23rd ACM/IEEE Design Automation Conference. Las Vegas, 1986

1985

Future directions for DA machine research (panel session).

[BibT_eX]

[DOI]

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

A Class of Cellular Computer Architectures to Support Physical Design Automation (Vlsi Layout, Integrated Circuit, Routing).

[BibT_eX]

[DOI]

PhD thesis, 1984

A Class of Cellular Architectures to Support Physical Design Automation.

[BibT_eX]

[DOI]

Trevor N. Mudge

Daniel E. Atkins

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1982

Cellular image processing techniques for VLSI circuit layout validation and routing.

[BibT_eX]

[DOI]

Proceedings of the 19th Design Automation Conference, 1982

1981

Case study of a VLSI design project: A simple inner product machine.

[BibT_eX]

[DOI]