Rituparna Choudhury

Orcid: 0000-0002-1273-009X

According to our database1, Rituparna Choudhury authored at least 6 papers between 2017 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2023
FPGA Implementation of Batch-Mode Depth-Pipelined Two Means Decision Tree.
IEEE Embed. Syst. Lett., March, 2023

2022
Hardware Implementation of Low Complexity High-speed Perceptron Block.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021
Efficient Hardware Implementation of Decision Tree Training Accelerator.
SN Comput. Sci., February, 2021

Training Accelerator for Two Means Decision Tree.
IEEE Trans. Very Large Scale Integr. Syst., 2021

FPGA Implementation of Low Complexity Hybrid Decision Tree Training Accelerator.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2017
Design and Implementation of Mixed Parallel and Dataflow Architecture for Intra-prediction Hardware in HEVC Decoder.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017


  Loading...