Rishad A. Shafik

Orcid: 0000-0001-5444-537X

Affiliations:
  • Newcastle University, School of Electrical and Electronic Engineering
  • University of Southampton, School of Electronics and Computer Science


According to our database1, Rishad A. Shafik authored at least 99 papers between 2008 and 2024.

Collaborative distances:

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Bibliography

2024
Exploring State Space and Reasoning by Elimination in Tsetlin Machines.
CoRR, 2024

MATADOR: Automated System-on-Chip Tsetlin Machine Design Generation for Edge Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Welcome Message from the Chairs.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2024

Design of Event-Driven Tsetlin Machines Using Safe Petri Nets.
Proceedings of the Application and Theory of Petri Nets and Concurrency, 2024

2023
Approximate digital-in analog-out multiplier with asymmetric nonvolatility and low energy consumption.
Integr., November, 2023

REDRESS: Generating Compressed Models for Edge Inference Using Tsetlin Machines.
IEEE Trans. Pattern Anal. Mach. Intell., September, 2023

A multi-step finite-state automaton for arbitrarily deterministic Tsetlin Machine learning.
Expert Syst. J. Knowl. Eng., May, 2023

A TEG-Based Non-Intrusive Ultrasonic System for Autonomous Water Flow Rate Measurement.
IEEE Trans. Sustain. Comput., 2023

Convolutional Tsetlin Machine-based Training and Inference Accelerator for 2-D Pattern Classification.
Microprocess. Microsystems, 2023

Contracting Tsetlin Machine with Absorbing Automata.
CoRR, 2023

An FPGA Architecture for Online Learning using the Tsetlin Machine.
CoRR, 2023

Energy-frugal and Interpretable AI Hardware Design using Learning Automata.
CoRR, 2023

Finite State Automata Design using 1T1R ReRAM Crossbar.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Variable Duty Cycle Pulse Generation for Low Complexity Randomization in Machine Learning.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

Nano-Magnetic Logic based Architecture for Edge Inference using Tsetlin Machine.
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023

IMBUE: In-Memory Boolean-to-CUrrent Inference ArchitecturE for Tsetlin Machines.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

Asynchronous Control for Tsetlin Machine with Binary Memristor-Transistor Array.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Logic-Based Machine Learning with Reproducible Decision Model Using the Tsetlin Machine.
Proceedings of the 12th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications, 2023

Stateful Energy Management for Multi-Source Energy Harvesting Transient Computing Systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
An FPGA Based Energy-Efficient Read Mapper With Parallel Filtering and In-Situ Verification.
IEEE ACM Trans. Comput. Biol. Bioinform., 2022

Logic-based intelligence for batteryless sensors.
Proceedings of the HotMobile '22: The 23rd International Workshop on Mobile Computing Systems and Applications, Tempe, Arizona, USA, March 9, 2022

Adaptive Intelligence for Batteryless Sensors Using Software-Accelerated Tsetlin Machines.
Proceedings of the 20th ACM Conference on Embedded Networked Sensor Systems, 2022

Automated Mapping of Asynchronous Circuits on FPGA under Timing Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Editable asynchronous control logic for SAR ADCs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

Cyclostationary Random Number Sequences for the Tsetlin Machine.
Proceedings of the Advances and Trends in Artificial Intelligence. Theory and Practices in Artificial Intelligence, 2022

Automated Synthesis of Asynchronous Tsetlin Machines on FPGA.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022

SenSig: Practical IoT Sensor Fingerprinting Using Calibration Data.
Proceedings of the IEEE European Symposium on Security and Privacy, 2022

Hardware-Algorithm Codesign for Fast and Energy Efficient Approximate String Matching on FPGA for Computational Biology.
Proceedings of the 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2022

Runtime Energy Minimization of Distributed Many-Core Systems using Transfer Learning.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
CORAL: Verification-Aware OpenCL Based Read Mapper for Heterogeneous Systems.
IEEE ACM Trans. Comput. Biol. Bioinform., 2021

QoS-Aware Power Minimization of Distributed Many-Core Servers using Transfer Q-Learning.
CoRR, 2021

Low-Power Audio Keyword Spotting using Tsetlin Machines.
CoRR, 2021

Run-time Configurable Approximate Multiplier using Significance-Driven Logic Compression.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Optimized Multi-Memristor Model based Low Energy and Resilient Current-Mode Multiplier Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Low-Latency Asynchronous Logic Design for Inference at the Edge.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

PLEDGER: Embedded Whole Genome Read Mapping using Algorithm-HW Co-design and Memory-aware Implementation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Self-timed Reinforcement Learning using Tsetlin Machine.
Proceedings of the 27th IEEE International Symposium on Asynchronous Circuits and Systems, 2021

2020
PARMA: Parallelization-Aware Run-Time Management for Energy-Efficient Many-Core Systems.
IEEE Trans. Computers, 2020

Amdahl's law in the context of heterogeneous many-core systems - a survey.
IET Comput. Digit. Tech., 2020

A Novel Multi-step Finite-State Automaton for Arbitrarily Deterministic Tsetlin Machine Learning.
Proceedings of the Artificial Intelligence XXXVII, 2020

Dynamics of Time-Domain Power-Elastic Circuits for Pervasive Machine Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Accelerated Filtering and in situ Verification for Energy-Optimized Genome Read Mapping.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Explainability and Dependability Analysis of Learning Automata based AI Hardware.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

Self-Amplifying Current-Mode Multiplier Design using a Multi-Memristor Crossbar Cell Structure.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

SPICE Modeling and Characterization of Filament Formation Perovskite Memristors.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

From Arithmetic to Logic based AI: A Comparative Analysis of Neural Networks and Tsetlin Machine.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar Architecture.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

REPUTE: An OpenCL based Read Mapping Tool for Embedded Genomics.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Neural Network Design for Energy-Autonomous AI Applications using Temporal Encoding.
CoRR, 2019

A Pulse Width Modulation based Power-elastic and Robust Mixed-signal Perceptron Design.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Speedup and Power Scaling Models for Heterogeneous Many-Core Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018

Real-Power Computing.
IEEE Trans. Computers, 2018

Significance-Driven Logic Compression for Energy-Efficient Multiplier Design.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Model-Free Runtime Management of Concurrent Workloads for Energy-Efficient Many-Core Heterogeneous Systems.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

MEMS-Based Runtime Idle Energy Minimization for Bursty Workloads in Heterogeneous Many-Core Systems.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Non-invasive Blood Glucose Estimation Methodology Using Predictive Glucose Homeostasis Models.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017
Voltage, Throughput, Power, Reliability, and Multicore Scaling.
Computer, 2017

Energy-efficient approximate wallace-tree multiplier using significance-driven logic compression.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017

Speedup and Parallelization Models for Energy-Efficient Many-Core Systems Using Performance Counters.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

Welcome Message.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Lifetime reliability characterization of N/MEMS used in power gating of digital integrated circuits.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

Energy-efficient approximate multiplier design using bit significance-driven logic compression.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Machine learning for run-time energy optimisation in many-core systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Significance-driven adaptive approximate computing for energy-efficient image processing applications: special session paper.
Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017

2016
Learning Transfer-Based Adaptive Energy Minimization in Embedded Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Power-Aware Performance Adaptation of Concurrent Applications in Heterogeneous Many-Core Systems.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

K-nearest neighbor based methodology for accurate diagnosis of diabetes mellitus.
Proceedings of the Sixth International Symposium on Embedded Computing and System Design, 2016

Design and implementation of an adaptive learning system: An MSc project experience.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

Challenges and opportunities in research and education of heterogeneous many-core applications.
Proceedings of the 11th European Workshop on Microelectronics Education, 2016

Power-Normalized Performance Optimization of Concurrent Many-Core Applications.
Proceedings of the 16th International Conference on Application of Concurrency to System Design, 2016

Power and Energy Normalized Speedup Models for Heterogeneous Many Core Computing.
Proceedings of the 16th International Conference on Application of Concurrency to System Design, 2016

2015
A Low-Cost Unified Design Methodology for Secure Test and Intellectual Property Core Protection.
IEEE Trans. Reliab., 2015

Application-specific memory protection policies for energy-efficient reliable design.
Proceedings of the 2015 International Symposium on Rapid System Prototyping, 2015

Adaptive energy minimization of embedded heterogeneous systems using regression-based learning.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

Adaptive Energy Minimization of OpenMP Parallel Applications on Many-Core Systems.
Proceedings of the 6th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 4th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2015

Workload uncertainty characterization and adaptive frequency scaling for energy minimization of embedded systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Energy-Efficient and High-Speed Robust System Design for Remote Cardiac Health Monitoring.
J. Low Power Electron., 2014

Verilog-A Based Effective Complementary Resistive Switch Model for Simulations and Analysis.
IEEE Embed. Syst. Lett., 2014

A low power and robust carbon nanotube 6T SRAM design with metallic tolerance.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Reinforcement Learning-Based Inter- and Intra-Application Thermal Optimization for Lifetime Improvement of Multicore Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014


2013
DeSyRe: On-demand system reliability.
Microprocess. Microsystems, 2013

Low Power and Robust Binary Tree SRAM Design for Embedded Systems.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

A Novel Physical Synthesis Methodology in the VLSI Design Automation by Introducing Dynamic Library Concept.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

A Novel and Unified Digital IC Design and Automation Methodology with Reduced NRE Cost and Time-to-Market.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Lifetime Reliability-Aware Checkpointing Mechanism: Modelling and Analysis.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Energy-Efficient and High-Speed Robust Channel Identification Methodology to Solve Permutation Indeterminacy in ICA for Artifacts Removal from ECG in Remote Healthcare.
Proceedings of the 2013 International Symposium on Electronic System Design, 2013

Software Modification Aided Transient Error Tolerance for Embedded Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A fast and Effective DFT for test and diagnosis of power switches in SoCs.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
System-level design optimization of reliable and low power multiprocessor system-on-chip.
Microelectron. Reliab., 2012

RAEF: A Power Normalized System-Level Reliability Analysis and Estimation Framework.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A Closed-Loop Control Strategy for Glucose Control in Artificial Pancreas Systems.
Proceedings of the International Symposium on Electronic System Design, 2012

STEP: a unified design methodology for secure test and IP core protection.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

2011
Reliability analysis of on-chip communication architectures: An MPEG-2 video decoder case study.
Microprocess. Microsystems, 2011

2010
Investigation into low power and reliable system-on-chip design.
PhD thesis, 2010

Soft error-aware design optimization of low power and time-constrained embedded systems.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Soft Error-Aware Voltage Scaling Technique for Power Minimization in Application-Specific Multiprocessor System-on-Chip.
J. Low Power Electron., 2009

2008
SystemC-Based Minimum Intrusive Fault Injection Technique with Improved Fault Representation.
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

MPEG-based Performance Comparison between Network-on-Chip and AMBA MPSoC.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008


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