Rinkle Jain

According to our database1, Rinkle Jain authored at least 17 papers between 2006 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
28.6 An 87% Efficient 2V-Input, 200A Voltage Regulator Chiplet Enabling Vertical Power Delivery in Multi-kW Systems-on-Package.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023
A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks.
IEEE J. Solid State Circuits, May, 2023

A 90.4% Peak Efficiency 48-to-1-V GaN/Si Hybrid Converter With Three-Level Hybrid Dickson Topology and Gradient Descent Run-Time Optimizer.
IEEE J. Solid State Circuits, 2023

2021
A 12MHz/38.4MHz Fast Start-Up Crystal Oscillator using Impedance Guided Chirp Injection in 22nm FinFET CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2019
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization.
IEEE J. Solid State Circuits, 2019

2018
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2018

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2017
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2016
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator.
IEEE J. Solid State Circuits, 2016

2015
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2015

8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS.
IEEE J. Solid State Circuits, 2014

5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A staircase conductance modulation scheme for input-current-shaping in switched-capacitor DC-DC converters.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2011
A novel control technique to eliminate output-voltage-ripple in switched-capacitor DC-DC converters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2006
A Comprehensive Analysis of Hybrid Phase-Modulated Converter With Current-Doubler Rectifier and Comparison With Its Center-Tapped Counterpart.
IEEE Trans. Ind. Electron., 2006


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