Rimon Ikeno

Orcid: 0000-0003-0527-4601

According to our database1, Rimon Ikeno authored at least 14 papers between 1998 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
Analysis of Light Intensity and Charge Holding Time Dependence of Pinned Photodiode Full Well Capacity.
Sensors, October, 2023

A 3.96μm, 124dB Dynamic Range, 6.2mW Stacked Digital Pixel Sensor with Monochrome and Near-Infrared Dual-Channel Global Shutter Capture.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

2018
Digitally-Controlled Compensation Current Injection to ATE Power Supply for Emulation of Customer Environment.
J. Electron. Test., 2018

A Consideration on LUT Linearization of Stochastic ADC in Sub-Ranging Architecture.
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
Extension of power supply impedance emulation method on ATE for multiple power domain.
Proceedings of the 22nd IEEE European Test Symposium, 2017

2016
Power supply impedance emulation to eliminate overkills and underkills due to the impedance difference between ATE and customer board.
Proceedings of the 2016 IEEE International Test Conference, 2016

Experimental demonstration of stochastic comparators for fine resolution ADC without calibration.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015
A Technique for Analyzing On-Chip Power Supply Impedance.
Proceedings of the 24th IEEE Asian Test Symposium, 2015

2014
A Structured Routing Architecture for Practical Application of Character Projection Method in Electron-Beam Direct Writing.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2013
High-Throughput Electron Beam Direct Writing of VIA Layers by Character Projection with One-Dimensional VIA Characters.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

A structured routing architecture and its design methodology suitable for high-throughput electron beam direct writing with character projection.
Proceedings of the International Symposium on Physical Design, 2013

High-throughput electron beam direct writing of VIA layers by character projection using character sets based on one-dimensional VIA arrays with area-efficient stencil design.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2011
COOL interconnect low power interconnection technology for scalable 3D LSI design.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011

1998
One-Dimensional Analysis of Subthreshold Characteristics of SOI-MOSFET Considering Quantum Mechanical Effects.
VLSI Design, 1998


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