Rimantas Seinauskas

According to our database, Rimantas Seinauskas authored at least 18 papers between 1997 and 2018.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2018

Black box delay fault models for non-scan sequential circuits.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Liudas Motiejunas, Rimantas Seinauskas

Comput. Sci. Inf. Syst., 2018

2015

Path delay test generation at functional level.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

IET Comput. Digit. Tech., 2015

2013

Delay fault testing using partial multiple scan chains.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Microelectron. Reliab., 2013

Functional delay test generation approach using a software prototype of the circuit.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Comput. Sci. Inf. Syst., 2013

2012

Evaluation of testability enhancement using software prototype.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

IET Comput. Digit. Tech., 2012

2011

Functional fault models for non-scan sequential circuits.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Microelectron. Reliab., 2011

2009

Functional delay test generation based on software prototype.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Microelectron. Reliab., 2009

2008

Test generation at the algorithm-level for gate-level fault coverage.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Microelectron. Reliab., 2008

Development of Functional Delay Tests.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

2007

Functional Test Generation Based on Combined Random and Deterministic Search Methods.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Informatica, 2007

The Criteria of Functional Delay Test Quality Assessment.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

Transition Faults Testing Based on Functional Delay Tests.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Transition Fault Test Reuse.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

The Realization-Independent Testing Based on the Black Box Fault Models.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Informatica, 2005

Functional Test Generation Remote Tool.

Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas

Proceedings of the Eighth Euromicro Symposium on Digital Systems Design (DSD 2005), 30 August, 2005

2003

Identifying Legal and Illegal States in Synchronous Sequential Circuits Using Test Generation.

Eduardas Bareisa, Kestutis Motiejunas, Rimantas Seinauskas

Informatica, 2003

2001

Procedures for Selection of Validation Vectors on the Algorithm Level.

Vacius Jusas, Kestutis Paulikas, Rimantas Seinauskas

Proceedings of the 2nd Latin American Test Workshop, 2001

1997

A distance laboratory for computer-aided design.

Rimantas Seinauskas

Proceedings of the 1997 IEEE International Conference on Microelectronic Systems Education, 1997