Rijoy Mukherjee

Orcid: 0000-0002-8432-3418

According to our database1, Rijoy Mukherjee authored at least 12 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2024
Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis.
CoRR, 2024

2023
Attacks on Recent DNN IP Protection Techniques and Their Mitigation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

2022
A comprehensive survey of physical and logic testing techniques for Hardware Trojan detection and prevention.
J. Cryptogr. Eng., 2022

Novel Hardware Trojan Attack on Activation Parameters of FPGA-Based DNN Accelerators.
IEEE Embed. Syst. Lett., 2022

2021
APUF-BNN: An Automated Framework for Efficient Combinational Logic Based Implementation of Arbiter PUF through Binarized Neural Network.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020
Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure.
J. Hardw. Syst. Secur., 2020

SoK: Physical and Logic Testing Techniques for Hardware Trojan Detection.
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020

2017
Design of Testable Adder in Quantum-dot Cellular Automata with Fault Secure Logic.
Microelectron. J., 2017

2016
On the reliability of majority logic structure in quantum-dot cellular automata.
Microelectron. J., 2016

A Processing In-Memory Realization Using QCA: Proposal and Implementation.
CoRR, 2016

Towards Designing Reliable Universal QCA Logic in the Presence of Cell Deposition Defect.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2014
Design of Fault Tolerant Universal Logic in QCA.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014


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