Ridha Djemal

According to our database1, Ridha Djemal authored at least 20 papers between 1996 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Neurological Disorder Diagnosis through Deep Residual Network-based EEG Signal Analysis.
Proceedings of the 7th IEEE International Conference on Advanced Technologies, 2024

2023
Enhancing Performances of Intelligent EEG Signal Processing for Epilepsy Diagnosis.
Proceedings of the 2023 IEEE International Conference on Design, 2023

2021
Enhanced parallel CFAR architecture with sharing resources using FPGA.
Int. J. Embed. Syst., 2021

2020
Comprehensive review on brain-controlled mobile robots and robotic arms based on electroencephalography signals.
Intell. Serv. Robotics, 2020

A Dynamic Filtering DF-RNN Deep-Learning-Based Approach for EEG-Based Neurological Disorders Diagnosis.
IEEE Access, 2020

EEG Person Identification Using Facenet, LSTM-RNN and SVM.
Proceedings of the 17th International Multi-Conference on Systems, Signals & Devices, 2020

2018
Single-channel-based automatic drowsiness detection architecture with a reduced number of EEG features.
Microprocess. Microsystems, 2018

2017
A Hardware/Software Prototype of EEG-based BCI System for Home Device Control.
J. Signal Process. Syst., 2017

2016
Online Adaptive Filters to Classify Left and Right Hand Motor Imagery.
Proceedings of the 9th International Joint Conference on Biomedical Engineering Systems and Technologies (BIOSTEC 2016), 2016

A DWT-entropy-ANN based architecture for epilepsy diagnosis using EEG signals.
Proceedings of the 2nd International Conference on Advanced Technologies for Signal and Image Processing, 2016

2014
An embedded implementation of home devices control system based on brain computer interface.
Proceedings of the 26th International Conference on Microelectronics, 2014

2013
An Embedded System Architecture of Automatic censored Ordered Statistic Detector Techniques.
J. Circuits Syst. Comput., 2013

An adaptive CFAR embedded system architecture for target detection.
Des. Autom. Embed. Syst., 2013

Design of priority-based active queue management for a high-performance IP switch.
Comput. Electr. Eng., 2013

2009
Efficient hardware architecture of 2D-scan-based wavelet watermarking for image and video.
Comput. Stand. Interfaces, 2009

2005
A novel formal verification approach for RTL hardware IP cores.
Comput. Stand. Interfaces, 2005

2004
High performance architecture of integrated protocols for encoded video application.
Comput. Stand. Interfaces, 2004

2001
A Flow Control Approach for Encoded Video Applications Over ATM Network.
Proceedings of the Sixth IEEE Symposium on Computers and Communications (ISCC 2001), 2001

2000
Rapid prototyping of an ATM programmable associative operator.
J. Syst. Archit., 2000

1996
Toward reconfigurable associative architecture for high speed communication operators.
Proceedings of the IEEE Symposium and Workshop on Engineering of Computer Based Systems (ECBS'96), 1996


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