Rico Backasch

According to our database1, Rico Backasch authored at least 7 papers between 2013 and 2015.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2015
Automated composition and execution of hardware-accelerated operator graphs.
Proceedings of the 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2015

An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

An architectural template for composing application specific datapaths at runtime.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015

2014
Identifying homogenous reconfigurable regions in heterogeneous FPGAs for module relocation.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Parallel and Pipelined Filter Operator for Hardware-Accelerated Operator Graphs in Semantic Web Databases.
Proceedings of the 14th IEEE International Conference on Computer and Information Technology, 2014

2013
Runtime verification for multicore SoC with high-quality trace data.
ACM Trans. Design Autom. Electr. Syst., 2013

Custom Reconfigurable Architecture Based on Virtex 5 Lookup Tables.
Proceedings of the Architecture of Computing Systems - ARCS 2013, 2013


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