Richard Wong
According to our database1,
Richard Wong
authored at least 37 papers
between 1998 and 2023.
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Bibliography
2023
EURASIP J. Wirel. Commun. Netw., December, 2023
2020
2019
A Fully Integrated Digital LDO With Built-In Adaptive Sampling and Active Voltage Positioning Using a Beat-Frequency Quantizer.
IEEE J. Solid State Circuits, 2019
Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies.
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
Microelectron. Reliab., 2018
Microelectron. Reliab., 2018
A fully integrated 40pF output capacitor beat-frequency-quantizer-based digital LDO with built-in adaptive sampling and active voltage positioning.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2016
Proceedings of the SIGGRAPH ASIA 2016, Macao, December 5-8, 2016 - Posters, 2016
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016
2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Logic soft error study with 800-MHz DDR3 SDRAMs in 3x nm using proton and neutron beams.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2014
Single-Event Transient Measurements on a DC/DC Pulse Width Modulator Using Heavy Ion, Proton, and Pulsed Laser.
J. Electron. Test., 2014
New approaches for synthesis of redundant combinatorial logic for selective fault tolerance.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
2013
Soft error tolerant Content Addressable Memories (CAMs) using error detection codes and duplication.
Microprocess. Microsystems, 2013
J. Electron. Test., 2013
Proceedings of the IEEE 19th Pacific Rim International Symposium on Dependable Computing, 2013
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
Performance, Metastability, and Soft-Error Robustness Trade-offs for Flip-Flops in 40 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
J. Electron. Test., 2012
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012
2011
ACM Trans. Design Autom. Electr. Syst., 2011
IEEE J. Solid State Circuits, 2011
Design method of NOR-type comparison circuit in CAM with ground bounce noise considerations.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011
Quantitative SEU Fault Evaluation for SRAM-Based FPGA Architectures and Synthesis Algorithms.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the 16th European Test Symposium, 2011
Performance, metastability and soft-error robustness tradeoffs for flip-flops in 40nm CMOS.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Minimizing Soft Errors in TCAM Devices: A Probabilistic Approach to Determining Scrubbing Intervals.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
1998
Microprocess. Microsystems, 1998