Richard E. Matick
According to our database1,
Richard E. Matick
authored at least 11 papers
between 1984 and 2009.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2009
IEEE J. Solid State Circuits, 2009
2008
A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier.
IEEE J. Solid State Circuits, 2008
2007
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
2003
Comparison of analytic performance models using closed mean-value analysis versus open-queuing theory for estimating cycles per instruction of memory hierarchies.
IBM J. Res. Dev., 2003
2001
Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory.
IBM J. Res. Dev., 2001
1998
IBM J. Res. Dev., 1998
1989
Architecture, Design, and Operating Characteristics of a 12-ns CMOS Functional Cache Chip.
IBM J. Res. Dev., 1989
1986
IBM Syst. J., 1986
1984