Richard Dorrance

According to our database, Richard Dorrance authored at least 20 papers between 2011 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications.

Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Niranjan Gowda, Brent R. Carlton

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

An Energy-Efficient Bayesian Neural Network Accelerator With CiM and a Time-Interleaved Hadamard Digital GRNG Using 22-nm FinFET.

Richard Dorrance, Deepak Dasalukunte, Hechen Wang, Renzhi Liu, Brent R. Carlton

IEEE J. Solid State Circuits, October, 2023

A 2-Gb/s UWB Transceiver for Short-Range Reconfigurable FDD Wireless Networks.

Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Timothy F. Cox, Rinkle Jain, Tolga Acikalin, Zhen Zhou, Tae-Young Yang, Johanny Escobar-Pelaez, Shuhei Yamada, Kenneth P. Foust, Brent R. Carlton

IEEE J. Solid State Circuits, May, 2023

A Charge Domain SRAM Compute-in-Memory Macro With C-2C Ladder-Based 8-Bit MAC Unit in 22-nm FinFET Process for Edge Inference.

Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Dan Lake, Brent R. Carlton

IEEE J. Solid State Circuits, 2023

2022

Low latency communication over commercially available LTE and remote driving.

Andrey Belogolovy, Deepak Dasalukunte, Richard Dorrance, Evgeny Stupachenko, Xue Zhang

CoRR, 2022

A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference.

Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Xiaosen Liu, Dan Lake, Brent R. Carlton, May Wu

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

An Analysis of Complex-Valued CNNs for RF Data-Driven Wireless Device Classification.

Jun Chen, Weng-Keen Wong, Bechir Hamdaoui, Abdurrahman Elmaghbub, Kathiravetpillai Sivanesan, Richard Dorrance, Lily L. Yang

Proceedings of the IEEE International Conference on Communications, 2022

2021

A Vector Processor for Mean Field Bayesian Channel Estimation.

Deepak Dasalukunte, Richard Dorrance, Le Liang, Lu Lu

IEEE Trans. Very Large Scale Integr. Syst., 2021

2020

An 802.11ba-Based Wake-Up Radio Receiver With Wi-Fi Transceiver Integration.

Renzhi Liu, K. T. Asma Beevi, Richard Dorrance, Deepak Dasalukunte, Vinod Kristem, Mario A. Santana Lopez, Alexander W. Min, Shahrnaz Azizi, Minyoung Park, Brent R. Carlton

IEEE J. Solid State Circuits, 2020

A Digital Root Based Modular Reduction Technique for Power Efficient, Fault Tolerance in FPGAs.

Richard Dorrance, Andrey Belogolovy, Hechen Wang, Xue Zhang

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019

An Ultra-Low Power, Fully Integrated Wake-Up Receiver and Digital Baseband with All-Digital Impairment Correction and -92.4dBm Sensitivity for 802.11ba.

Richard Dorrance, Renzhi Liu, K. T. Asma Beevi, Deepak Dasalukunte, Mario A. Santana Lopez, Vinod Kristem, Shahrnaz Azizi, Brent R. Carlton

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

2018

802.11g/n Compliant Fully Integrated Wake-Up Receiver With -72-dBm Sensitivity in 14-nm FinFET CMOS.

Erkan Alpman, Ahmad Khairi, Richard Dorrance, Minyoung Park, V. Srinivasa Somayazulu, Jeffrey R. Foerster, Ashoke Ravi, Jeyanandh Paramesh, Stefano Pellerano

IEEE J. Solid State Circuits, 2018

A cm-scale self-powered intelligent and secure IoT edge mote featuring an ultra-low-power SoC in 14nm tri-gate CMOS.

Tanay Karnik, Dileep Kurian, Paolo A. Aseron, Richard Dorrance, Erkan Alpman, Angela Nicoara, Roman Popov, Leonid Azarenkov, Mikhail J. Moiseev, Li Zhao, Santosh Ghosh, Rafael Misoczki, Ankit Gupta, M. Akhila, Sriram Muthukumar, Saurabh Bhandari, Satish Yada, Kartik Jain, Robert Flory, Chanitnan Kanthapanit, Eduardo Quijano, Bradley Jackson, Hao Luo, Suhwan Kim, Vaibhav A. Vaidya, Adel Elsherbini, Renzhi Liu, Farhana Sheikh, Omesh Tickoo, Ilya Klotchkov, Manoj R. Sastry, Sheldon Sun, Mukesh Bhartiya, Anuradha Srinivasan, Yatin Hoskote, Hong Wang, Vivek De

Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2016

A 190GFLOPS/W DSP for energy-efficient sparse-BLAS in embedded IoT.

Richard Dorrance, Dejan Markovic

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2015

An Energy-Efficient Sparse-BLAS Coprocessor using STT-MRAM.

Richard Dorrance

PhD thesis, 2015

2014

A scalable sparse matrix-vector multiplication kernel for energy-efficient sparse-blas on FPGAs.

Richard Dorrance, Fengbo Ren, Dejan Markovic

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013

A single-precision compressive sensing signal reconstruction engine on FPGAs.

Fengbo Ren, Richard Dorrance, Wenyao Xu, Dejan Markovic

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

2012

A body-voltage-sensing-based short pulse reading circuit for spin-torque transfer RAMs (STT-RAMs).

Fengbo Ren, Henry Park, Richard Dorrance, Yuta Toriyama, Chih-Kong Ken Yang, Dejan Markovic

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Analysis of STT-RAM cell design with multiple MTJs per access.

Henry Park, Richard Dorrance, Amr Amin Hafez, Fengbo Ren, Dejan Markovic, Chih-Kong Ken Yang

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Scalability and design-space analysis of a 1T-1MTJ memory cell.

Richard Dorrance, Fengbo Ren, Yuta Toriyama, Amr Amin Hafez, Chih-Kong Ken Yang, Dejan Markovic

Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011