Riccardo Della Sala

Orcid: 0000-0001-9990-4875

According to our database1, Riccardo Della Sala authored at least 25 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Rail to Rail ICMR and High Performance ULV Standard-Cell-Based Comparator for Biomedical and IoT Applications.
IEEE Access, 2024

A Novel High Performance Standard-Cell Based ULV OTA Exploiting an Improved Basic Amplifier.
IEEE Access, 2024

On the Feasibility of Cascode and Regulated Cascode Amplifier Stages in ULV Circuits Exploiting MOS Transistors in Deep Subthreshold Operation.
IEEE Access, 2024

A Novel Technique to Design Ultra-Low Voltage and Ultra-Low Power Inverter-Based OTAs.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024

Enhancing Performance of Ultra-Low Voltage Body-Driven Comparators Through Clocked Supply Voltage.
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024

2023
A Novel FPGA Implementation of the NAND-PUF with Minimal Resource Usage and High Reliability.
Cryptogr., June, 2023

A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages.
Int. J. Circuit Theory Appl., May, 2023

An Improved Strong Arm Comparator With Integrated Static Preamplifier.
IEEE Access, 2023

Exploiting the DD-Cell as an Ultra-Compact Entropy Source for an FPGA-Based Re-Configurable PUF-TRNG Architecture.
IEEE Access, 2023

A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations.
IEEE Access, 2023

Robust Body Biasing Techniques for Dynamic Comparators.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing.
Proceedings of the 18th Conference on Ph.D Research in Microelectronics and Electronics, 2023

On Enhancing the Throughput of the Latched Ring Oscillator TRNG on FPGA.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

2022
Enabling ULV Fully Synthesizable Analog Circuits: The BA Cell, a Standard-Cell-Based Building Block for Analog Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Novel Ultra-Compact FPGA-Compatible TRNG Architecture Exploiting Latched Ring Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

High-Throughput FPGA-Compatible TRNG Architecture Exploiting Multistimuli Metastable Cells.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Novel Differential to Single-Ended Converter for Ultra-Low-Voltage Inverter-Based OTAs.
IEEE Access, 2022

The DD-Cell: a Double Side Entropic Source exploitable as PUF and TRNG.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Sub-μW Front-End Low Noise Amplifier for Neural Recording Applications.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

High-efficiency 0.3V OTA in CMOS 130nm technology using current mirrors with gain.
Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

2021
A Novel Ultra-Compact FPGA PUF: The DD-PUF.
Cryptogr., 2021

SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks.
Cryptogr., 2021

2019
Area-Efficient Low-Power Bandpass Gm-C Filter for Epileptic Seizure Detection in 130nm CMOS.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019


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