Riccardo Cattaneo
Orcid: 0000-0002-1520-4271Affiliations:
- Politecnico di Milano, Italy
According to our database1,
Riccardo Cattaneo
authored at least 22 papers
between 2012 and 2016.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2016
ACM Trans. Archit. Code Optim., 2016
A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016
2015
On the role of polyhedral analysis in high performance reconfigurable hardware based computing systems.
PhD thesis, 2015
On how to efficiently accelerate brain network analysis on FPGA-based computing system.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
A multiobjective reconfiguration-aware scheduler for FPGA-based heterogeneous architectures.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Explicitly isolating data and computation in high level synthesis: the role of polyhedral framework.
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2015
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 International Conference on Hardware/Software Codesign and System Synthesis, 2015
2014
FPGA-Based Design Using the FASTER Toolchain: The Case of STM Spear Development Board.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
2013
Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013
A framework for effective exploitation of partial reconfiguration in dataflow computing.
Proceedings of the 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, 2013
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
Proceedings of the 2012 Workshop on Managing Systems Automatically and Dynamically, 2012
An Enhanced Relocation Manager to Speedup Core Allocation in FPGA-based Reconfigurable Systems.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012