Riccardo Cantoro
Orcid: 0000-0002-1745-5293Affiliations:
- Politécnico di Torino, Italy
According to our database1,
Riccardo Cantoro
authored at least 82 papers
between 2013 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Fault Grading Techniques for Evaluating Software-Based Self-Test with Respect to Small Delay Defects.
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test.
Proceedings of the IEEE European Test Symposium, 2024
Special Session: Software-Based Self-Test Generation for RISC-V - Stuck-At Generation, Functional Cell-Aware Untestability, and FPGA Demonstration -.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2024
Proceedings of the 27th International Symposium on Design & Diagnostics of Electronic Circuits & Systems, 2024
2023
Automating the Generation of Programs Maximizing the Repeatable Constant Switching Activity in Microprocessor Units via MaxSAT.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., October, 2023
Automating the Generation of Programs Maximizing the Sustained Switching Activity in Microprocessor units via Evolutionary Techniques.
Microprocess. Microsystems, April, 2023
Functional Testing with STLs: A Step Towards Reliable RISC-V-based HPC Commodity Clusters.
Proceedings of the High Performance Computing, 2023
Proceedings of the Machine Learning, Optimization, and Data Science, 2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
On the integration and hardening of Software Test Libraries in Real-Time Operating Systems.
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE European Test Symposium, 2023
A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.
Proceedings of the IEEE European Test Symposium, 2023
Targeting different defect-oriented fault models in IC testing: an experimental approach.
Proceedings of the 26th Euromicro Conference on Digital System Design, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Automatic Identification of Functionally Untestable Cell-Aware Faults in Microprocessors.
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
Proceedings of the 32nd IEEE Asian Test Symposium, 2023
2022
Exploiting post-silicon debug hardware to improve the fault coverage of Software Test Libraries.
Proceedings of the 40th IEEE VLSI Test Symposium, 2022
Runtime Test Solution for Adaptive Aging Compensation and Fail Operational Safety mode.
Proceedings of the IEEE International Reliability Physics Symposium, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
Microcontroller Performance Screening: Optimizing the Characterization in the Presence of Anomalous and Noisy Data.
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
A comparative overview of ATPG flows targeting traditional and cell-aware fault models.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Effective techniques for automatically improving the transition delay fault coverage of Self-Test Libraries.
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the IEEE European Test Symposium, 2022
Proceedings of the IEEE European Test Symposium, 2022
Improving the Fault Resilience of Neural Network Applications Through Security Mechanisms.
Proceedings of the 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2022
Proceedings of the IEEE 31st Asian Test Symposium, 2022
2021
Towards the Integration of Reliability and Security Mechanisms to Enhance the Fault Resilience of Neural Networks.
IEEE Access, 2021
New Techniques for the Automatic Identification of Uncontrollable Lines in a CPU Core.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021
Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage Improvement.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 26th IEEE European Test Symposium, 2021
Maximizing the Switching Activity of Different Modules Within a Processor Core via Evolutionary Techniques.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
Effective SAT-based Solutions for Generating Functional Sequences Maximizing the Sustained Switching Activity in a Pipelined Processor.
Proceedings of the 30th IEEE Asian Test Symposium, 2021
2020
IEEE Trans. Emerg. Top. Comput., 2020
A Novel Sequence Generation Approach to Diagnose Faults in Reconfigurable Scan Networks.
IEEE Trans. Computers, 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the IEEE Latin-American Test Symposium, 2020
Machine Learning based Performance Prediction of Microcontrollers using Speed Monitors.
Proceedings of the IEEE International Test Conference, 2020
Proceedings of the IEEE International Test Conference, 2020
Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs.
Proceedings of the IEEE European Test Symposium, 2020
Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020
2019
An Enhanced Evolutionary Technique for the Generation of Compact Reconfigurable Scan-Network Tests.
J. Circuits Syst. Comput., 2019
Proceedings of the 24th IEEE European Test Symposium, 2019
On-line Testing for Autonomous Systems driven by RISC-V Processor Design Verification.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Non-Intrusive Self-Test Library for Automotive Critical Applications: Constraints and Solutions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
J. Low Power Electron., 2018
J. Electron. Test., 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the VLSI-SoC: Design and Engineering of Electronics Systems Based on New Computing Paradigms, 2018
About on-line functionally untestable fault identification in microprocessor cores for safety-critical applications.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
Proceedings of the IEEE International Test Conference, 2018
A Semi-Formal Technique to Generate Effective Test Sequences for Reconfigurable Scan Networks.
Proceedings of the IEEE International Test Conference in Asia, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test.
Proceedings of the 21st IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2018
2017
PhD thesis, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
Proceedings of the 18th IEEE Latin American Test Symposium, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Computers, 2016
Observability solutions for in-field functional test of processor-based systems: A survey and quantitative test case evaluation.
Microprocess. Microsystems, 2016
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Thermal issues in test: An overview of the significant aspects and industrial practice.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Proceedings of the 2016 IEEE International Test Conference, 2016
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016
Proceedings of the 25th IEEE Asian Test Symposium, 2016
2015
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015
Exploiting Evolutionary Computation in an Industrial Flow for the Development of Code-Optimized Microprocessor Test Programs.
Proceedings of the Genetic and Evolutionary Computation Conference, 2015
Software-based self-test techniques of computational modules in dual issue embedded processors.
Proceedings of the 20th IEEE European Test Symposium, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 24th IEEE Asian Test Symposium, 2015
2014
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014
2013
On the Functional Test of the Register Forwarding and Pipeline Interlocking Unit in Pipelined Processors.
Proceedings of the 14th International Workshop on Microprocessor Test and Verification, 2013