Ricardo Quislant

Orcid: 0000-0002-4705-7042

According to our database1, Ricardo Quislant authored at least 29 papers between 2007 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Exploring multiprocessor approaches to time series analysis.
J. Parallel Distributed Comput., 2024

MATSA: An MRAM-Based Energy-Efficient Accelerator for Time Series Analysis.
IEEE Access, 2024

2023
Time series analysis acceleration with advanced vectorization extensions.
J. Supercomput., June, 2023

2022
Speculative Barriers With Transactional Memory.
IEEE Trans. Computers, 2022

TraTSA: A Transprecision Framework for Efficient Time Series Analysis.
J. Comput. Sci., 2022

Accelerating Time Series Analysis via Processing using Non-Volatile Memories.
CoRR, 2022

Exploiting Vector Extennsions to Accelerate Time Series Analysis.
Proceedings of the 30th Euromicro International Conference on Parallel, 2022

Exploiting Near-Data Processing to Accelerate Time Series Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

2020
Energy-Efficient Time Series Analysis Using Transprecision Computing.
Proceedings of the 32nd IEEE International Symposium on Computer Architecture and High Performance Computing, 2020

NATSA: A Near-Data Processing Accelerator for Time Series Analysis.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019
Improving hardware transactional memory parallelization of computational geometry algorithms using privatizing transactions.
J. Parallel Distributed Comput., 2019

2018
Privatizing transactions for Lee's algorithm in commercial hardware transactional memory.
J. Supercomput., 2018

2017
Lazy Irrevocability for Best-Effort Transactional Memory Systems.
IEEE Trans. Parallel Distributed Syst., 2017

Leveraging irrevocability to deal with signature saturation in hardware transactional memory.
J. Supercomput., 2017

Enhancing scalability in best-effort hardware transactional memory systems.
J. Parallel Distributed Comput., 2017

2016
Insights into the Fallback Path of Best-Effort Hardware Transactional Memory Systems.
Proceedings of the Euro-Par 2016: Parallel Processing, 2016

2015
Conflict Detection in Hardware Transactional Memory.
Proceedings of the Transactional Memory. Foundations, Algorithms, Tools, and Applications, 2015

2014
Improving Signature Behavior by Irrevocability in Transactional Memory Systems.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

Scalability Analysis of Signatures in Transactional Memory Systems.
Proceedings of the 26th IEEE International Symposium on Computer Architecture and High Performance Computing, 2014

2013
Hardware Signature Designs to Deal with Asymmetry in Transactional Data Sets.
IEEE Trans. Parallel Distributed Syst., 2013

LS-Sig: Locality-Sensitive Signatures for Transactional Memory.
IEEE Trans. Computers, 2013

Dealing with Reduction Operations Using Transactional Memory.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

Exploring Irregular Reduction Support in Transactional Memory.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

2011
Multiset signatures for transactional memory.
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011

Unified Locality-Sensitive Signatures for Transactional Memory.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

2010
Interval Filter: A Locality-Aware Alternative to Bloom Filters for Hardware Membership Queries by Interval Classification.
Proceedings of the Intelligent Data Engineering and Automated Learning, 2010

2009
Improving Signatures by Locality Exploitation for Transactional Memory.
Proceedings of the PACT 2009, 2009

2008
Teaching the Cache Memory System Using a Reconfigurable Approach.
IEEE Trans. Educ., 2008

2007
Simulating a Reconfigurable Cache System for Teaching Purposes.
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007


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