Ricardo Pires

Orcid: 0000-0003-4677-8435

According to our database1, Ricardo Pires authored at least 23 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2023
Revisiting predictions of movie economic success: random Forest applied to profits.
Multim. Tools Appl., October, 2023

2022
Differentiation between Epileptic and Psychogenic Nonepileptic Seizures in Electroencephalogram Using Wavelets and Support-Vector Machines.
Appl. Artif. Intell., 2022

2020
<i>SOMprocessor</i>: A high throughput FPGA-based architecture for implementing Self-Organizing Maps and its application to video processing.
Neural Networks, 2020

Movie films consumption in Brazil: an analysis of support vector machine classification.
AI Soc., 2020

2019
Human actions recognition in video scenes from multiple camera viewpoints.
Cogn. Syst. Res., 2019

2018
OFDM symbol identification by an unsupervised learning system under dynamically changing channel effects.
Neural Comput. Appl., 2018

An FPGA-based SOM circuit architecture for online learning of 64-QAM data streams.
Proceedings of the 2018 International Joint Conference on Neural Networks, 2018

Epileptic Seizure Prediction from EEG Signals Using Unsupervised Learning and a Polling-Based Decision Process.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2018, 2018

2015
TSV protection: Towards secure 3D-MPSoC.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

2013
An evolutive approach for designing thermal and performance-aware heterogeneous 3D-NoCs.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

Security-enhanced 3D communication structure for dynamic 3D-MPSoCs protection.
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

QoS 3D-HoC hybrid-on-chip communication structure for dynamic 3D-MPSoCs.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

3DMIA: a multi-objective artificial immune algorithm for 3D-MPSoC multi-application 3D-NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2013

2012
QoSS Hierarchical NoC-Based Architecture for MPSoC Dynamic Protection.
Int. J. Reconfigurable Comput., 2012

A Common Evaluation Setting for Just.Ask, Open Ephyra and Aranea QA systems
CoRR, 2012

Hybrid-on-chip communication architecture for dynamic MP-SoC protection.
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Multi-objective artificial immune algorithm for security-constrained multi-application NoC mapping.
Proceedings of the Genetic and Evolutionary Computation Conference, 2012

2011
Dynamic NoC-based architecture for MPSoC security implementation.
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011

2010
Implementation of QoSS (Quality-of-Security Service) for NoC-Based SoC Protection.
Trans. Comput. Sci., 2010

The LRD traffic impact on the NoC-based SoCs.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010

2004
Datapath BIST Insertion Using Pre-Characterized Area and Testability Data.
J. Electron. Test., 2004

2002
BIST Plan Optimization and Independent Input Test Register Insertion for Datapath Functional Units.
Proceedings of the 3rd Latin American Test Workshop, 2002

A Comparison Between Test Pattern Generation Strategies for Functional Units in BIST Applications.
Proceedings of the 3rd Latin American Test Workshop, 2002


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