Ricardo Fernández Pascual
Orcid: 0000-0002-2337-4369
According to our database1,
Ricardo Fernández Pascual
authored at least 38 papers
between 2003 and 2024.
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Bibliography
2024
Microprocess. Microsystems, 2024
Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory.
Proceedings of the 57th IEEE/ACM International Symposium on Microarchitecture, 2024
Proceedings of the IEEE International Symposium on Workload Characterization, 2024
2022
DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory.
IEEE Trans. Parallel Distributed Syst., 2022
J. Supercomput., 2022
Proceedings of the 30th Euromicro International Conference on Parallel, 2022
2020
IEEE Trans. Parallel Distributed Syst., 2020
J. Parallel Distributed Comput., 2020
2019
IEEE Trans. Parallel Distributed Syst., 2019
2017
To be silent or not: on the impact of evictions of clean data in cache-coherent multicores.
J. Supercomput., 2017
Concurr. Comput. Pract. Exp., 2017
Proceedings of the International Conference on Supercomputing, 2017
2016
Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study.
J. Supercomput., 2016
Stat. Methods Appl., 2016
J. Multivar. Anal., 2016
Proceedings of the Architecture of Computing Systems - ARCS 2016, 2016
2015
Proceedings of the 11th IEEE International Conference on e-Science, 2015
2014
Concurr. Comput. Pract. Exp., 2014
Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs.
Proceedings of the Euro-Par 2014: Parallel Processing Workshops, 2014
2012
ACM Trans. Archit. Code Optim., 2012
Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
An Experience of Early Initiation to Parallelism in the Computing Engineering Degree at the University of Murcia, Spain.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
2011
Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation.
Proceedings of the International Conference on Parallel Processing, 2011
2010
Dealing with Transient Faults in the Interconnection Network of CMPs at the Cache Coherence Level.
IEEE Trans. Parallel Distributed Syst., 2010
Proceedings of the 22st International Symposium on Computer Architecture and High Performance Computing, 2010
Proceedings of the 2010 International Conference on High Performance Computing, 2010
2008
Extending the TokenCMP Cache Coherence Protocol for Low Overhead Fault Tolerance in CMP Architectures.
IEEE Trans. Parallel Distributed Syst., 2008
Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors.
J. Parallel Distributed Comput., 2008
An Experimental Environment Validating the Suitability of CLI as an Effective Deployment Format for Embedded Systems.
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Proceedings of the High Performance Computing, 2008
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008
2007
An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology.
Parallel Comput., 2007
Proceedings of the 13st International Conference on High-Performance Computer Architecture (HPCA-13 2007), 2007
2005
Proceedings of the 13th Euromicro Workshop on Parallel, 2005
2003
Comput. Stat., 2003