Ricardo Chaves
Orcid: 0000-0002-4450-3983
According to our database1,
Ricardo Chaves
authored at least 74 papers
between 2003 and 2024.
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Bibliography
2024
Proceedings of the 27th Euromicro Conference on Digital System Design, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
Wirel. Networks, 2023
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023
Proceedings of the 31st IEEE International Conference on Network Protocols, 2023
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
Proceedings of the IEEE European Test Symposium, 2023
2022
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.
IEEE Access, 2022
Proceedings of the CF '22: 19th ACM International Conference on Computing Frontiers, Turin, Italy, May 17, 2022
2020
Future Internet, 2020
When Backscatter Communication Meets Vehicular Networks: Boosting Crosswalk Awareness.
IEEE Access, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020
2019
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019
2018
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018
Proceedings of the Progress in Cryptology - AFRICACRYPT 2018, 2018
2017
Ann. des Télécommunications, 2017
Pipelined FPGA coprocessor for elliptic curve cryptography based on residue number system.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the International Conference on ReConFigurable Computing and FPGAs, 2017
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017
Proceedings of the 2017 European Conference on Networks and Communications, 2017
2016
ACM Trans. Reconfigurable Technol. Syst., 2016
Integr., 2016
IACR Cryptol. ePrint Arch., 2016
Proceedings of the 35th IEEE Symposium on Reliable Distributed Systems, 2016
Proceedings of the Intelligent Environments 2016, 2016
Global Identity and Reachability Framework for Interoperable P2P Communication Services.
Proceedings of the 2016 conference on Innovations in Clouds, Internet and Networks, 2016
2015
Arithmetic-Based Binary-to-RNS Converter Modulo {2<sup>n</sup>±k} for jn-bit Dynamic Range.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IET Comput. Digit. Tech., 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
J. Signal Process. Syst., 2014
ROM-less RNS-to-binary converter moduli {2<sup>2n</sup> - 1, 2<sup>2n</sup> + 1, 2<sup>n</sup> - 3, 2<sup>n</sup> + 3}.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
Proceedings of the 9th Workshop on Embedded Systems Security, 2014
2013
On the Design of RNS Reverse Converters for the Four-Moduli Set ${\bf\{2^{\mmb n}+1, 2^{\mmb n}-1, 2^{\mmb n}, 2^{{\mmb n}+1}+1\}}$.
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
HotStream: Efficient Data Streaming of Complex Patterns to Multiple Accelerating Kernels.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013
Transparent Application Acceleration by Intelligent Scheduling of Shared Library Calls on Heterogeneous Systems.
Proceedings of the Parallel Processing and Applied Mathematics, 2013
A flexible shared library profiler for early estimation of performance gains in heterogeneous systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2013
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013
Proceedings of the 24th International Conference on Application-Specific Systems, 2013
2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
An improved RNS reverse converter for the {2<sup>2n+1</sup>-1, 2<sup>n</sup>, 2<sup>n</sup>-1} moduli set.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
2009
Proceedings of the FCCM 2009, 2009
2008
IEEE Trans. Very Large Scale Integr. Syst., 2008
Proceedings of the High Performance Computing for Computational Science, 2008
Proceedings of the High Performance Embedded Architectures and Compilers, 2008
Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
2007
Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures.
IET Comput. Digit. Tech., 2007
2006
Proceedings of the Embedded Computer Systems: Architectures, 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006
2005
Corrections to "A Universal Architecture for Designing Efficient Modulo 2<sup>n+1</sup> Multipliers".
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
2004
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004
2003
Proceedings of the 5th International Conference on Multimodal Interfaces, 2003
Towards tangibility in gameplay: building a tangible affective interface for a computer game.
Proceedings of the 5th International Conference on Multimodal Interfaces, 2003
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003
Proceedings of the Extended abstracts of the 2003 Conference on Human Factors in Computing Systems, 2003
Proceedings of the Second International Joint Conference on Autonomous Agents & Multiagent Systems, 2003