Ricardo Augusto da Luz Reis
Orcid: 0000-0001-5781-5858Affiliations:
- Federal University of Rio Grande do Sul, Porto Alegre, Brazil
According to our database1,
Ricardo Augusto da Luz Reis
authored at least 347 papers
between 1998 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the 15th IEEE Latin America Symposium on Circuits and Systems, 2024
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
Soft Error Assessment of UAV Control Algorithms Running in Resource-Constrained Microprocessors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024
2023
A Proof-of-Concept of a Multiple-Cell Upsets Detection Method for SRAMs in Space Applications.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
DeBaTE-FI: A Debugger-Based Fault Injector Infrastructure for IoT Soft Error Reliability Assessment.
Proceedings of the 9th IEEE World Forum on Internet of Things, 2023
An Energy-Efficient Interpolation Unit Targeting VVC Encoders with Approximate Adder.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Power and Performance Costs of Radiation-Hardened ML Inference Models Running on Edge Devices.
Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023
Proceedings of the 14th IEEE Latin America Symposium on Circuits and System, 2023
LEX - A Cell Switching Arcs Extractor: A Simple SPICE-Input Interface for Electrical Characterization.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Power, Performance and Reliability Evaluation of Multi-thread Machine Learning Inference Models Executing in Multicore Edge Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Impact on Radiation Robustness of Gate Mapping in FinFET Circuits under Work-function Fluctuation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
2022
The Impact of Soft Errors in Memory Units of Edge Devices Executing Convolutional Neural Networks.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
SOFIA: An automated framework for early soft error assessment, identification, and mitigation.
J. Syst. Archit., 2022
Exploring XOR-based Full Adders and decoupling cells to variability mitigation at FinFET technology.
Integr., 2022
Investigation of Hybrid Soft Error Mitigation Techniques for Applications running on Resource-constrained devices.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
Improving Soft Error Robustness of Full Adder Circuits with Decoupling Cell and Transistor Sizing.
Proceedings of the 35th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2022
Impact of Thread Parallelism on the Soft Error Reliability of Convolution Neural Networks.
Proceedings of the 13th IEEE Latin America Symposium on Circuits and System, 2022
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
A Lifetime of Physical Design Automation and EDA Education: ISPD 2022 Lifetime Achievement Award Bio.
Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022
Soft Error Reliability Assessment of Lightweight Cryptographic Algorithms for IoT Edge Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
An Extensive Soft Error Reliability Analysis of a Real Autonomous Vehicle Software Stack.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
Applying Lightweight Soft Error Mitigation Techniques to Embedded Mixed Precision Deep Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Evaluation of the soft error assessment consistency of a JIT-based virtual platform simulator.
IET Comput. Digit. Tech., 2021
Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021
Exploring Gate Mapping and Transistor Sizing to Improve Radiation Robustness: A C17 Benchmark Case-study.
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 22nd IEEE Latin American Test Symposium, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
The Impact of Precision Bitwidth on the Soft Error Reliability of the MobileNet Network.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
On the superiority of modularity-based clustering for determining placement-relevant clusters.
Integr., 2020
Proceedings of the 6th IEEE World Forum on Internet of Things, 2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
RAT: A Lightweight Architecture Independent System-Level Soft Error Mitigation Technique.
Proceedings of the VLSI-SoC: Design Trends, 2020
Proceedings of the 18th IEEE International New Circuits and Systems Conference, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the IEEE Latin-American Test Symposium, 2020
Work-Function Fluctuation Impact on the SET Response of FinFET-based Majority Voters.
Proceedings of the IEEE Latin-American Test Symposium, 2020
Gate Sizing for Power-Delay Optimization at Transistor-level Monolithic 3D-Integrated Circuits.
Proceedings of the 11th IEEE Latin American Symposium on Circuits & Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Soft Error Reliability Assessment of Neural Networks on Resource-constrained IoT Devices.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard.
Proceedings of the 28th European Signal Processing Conference, 2020
Soft Error Reliability Using Virtual Platforms - Early Evaluation of Multicore Systems
Springer, ISBN: 978-3-030-55703-4, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
IET Comput. Digit. Tech., 2019
Circuit-Level Techniques to Mitigate Process Variability and Soft Errors in FinFET Designs.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Efficient Soft Error Vulnerability Analysis Using Non-intrusive Fault Injection Techniques.
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019
Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing Algorithm.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the Internet of Things. A Confluence of Many Disciplines, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
FinFET Variability and Near-threshold operation: Impact on Full Adders design using XOR Blocks.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019
2018
Microelectron. Reliab., 2018
Microelectron. Reliab., 2018
Microelectron. Reliab., 2018
Evaluating the Impact of Process Variability and Radiation Effects on Different Transistor Arrangements.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
gem5-FIM: a flexible and scalable multicore soft error assessment framework to early reliability design space explorations.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
An automated methodology to fix electromigration violations on a customized design flow.
Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018
Pros and Cons of Schmitt Trigger Inverters to Mitigate PVT Variability on Full Adders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the Internet of Things. Information Processing in an Increasingly Connected World, 2018
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Exploring Multi-level Design to Mitigate Variability and Radiation Effects on 7nm FinFET Logic Cells.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
Extensive evaluation of programming models and ISAs impact on multicore soft error reliability.
Proceedings of the 55th Annual Design Automation Conference, 2018
2017
Microelectron. Reliab., 2017
Evaluation of radiation-induced soft error in majority voters designed in 7 nm FinFET technology.
Microelectron. Reliab., 2017
Proceedings of the VLSI-SoC: Opportunities and Challenges Beyond the Internet of Things, 2017
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Radiation sensitivity of XOR topologies in multigate technologies under voltage variability.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Impact of schmitt trigger inverters on process variability robustness of 1-Bit full adders.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
SET response of FinFET-based majority voter circuits under work-function fluctuation.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016
Microelectron. Reliab., 2016
Microelectron. Reliab., 2016
Selected Articles from the 6th International Workshop on CMOS Variability, Salvador, Bahia, Brazil, September 1-4, 2015.
J. Low Power Electron., 2016
Challenges of cell selection algorithms in industrial high performance microprocessor designs.
Integr., 2016
Leakage current analysis in static CMOS logic gates for a transistor network design approach.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016
Proceedings of the IEEE 7th Latin American Symposium on Circuits & Systems, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 on International Symposium on Physical Design, 2016
Proceedings of the 2016 on International Symposium on Physical Design, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Extending FreeRTOS to support dynamic and distributed mapping in multiprocessor systems.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
Microelectron. Reliab., 2015
Microelectron. Reliab., 2015
An Incremental Timing-Driven flow using quadratic formulation for detailed placement.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015
Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015
Multiple fault injection platform for SRAM-based FPGA based on ground-level radiation experiments.
Proceedings of the 16th Latin-American Test Symposium, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Reducing the signal Electromigration effects on different logic gates by cell layout optimization.
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Analyzing the Impact of Frequency and Diverse Path Delays in the Time Vulnerability Factor of Master-Slave D Flip-Flops.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015
Process variability in FinFET standard cells with different transistor sizing techniques.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Impact on performance, power, area and wirelength using electromigration-aware cells.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
A fast and scalable fault injection framework to evaluate multi/many-core soft error reliability.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015
Gate sizing and threshold voltage assignment for high performance microprocessor designs.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
Proceedings of the 2015 NASA/ESA Conference on Adaptive Hardware and Systems, 2015
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2014
Effective Method for Simultaneous Gate Sizing and $V$ th Assignment Using Lagrangian Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
Predictive evaluation of electrical characteristics of sub-22 nm FinFET technologies under device geometry variations.
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
Proceedings of the 27th Symposium on Integrated Circuits and Systems Design, 2014
Evaluating the impact of environment and physical variability on the ION current of 20nm FinFET devices.
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Proceedings of the 24th International Workshop on Power and Timing Modeling, 2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
Proceedings of the 15th Latin American Test Workshop, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Perfomance Improvement with Dedicated Transistor Sizing for MOSFET and FinFET Devices.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Thermal impact of 3D stacking and die thickness: Analysis and characterization of a memory-on-logic 3D circuit.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Analyzing the electromigration effects on different metal layers and different wire lengths.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
A systematic approach for analyzing and optimizing cell-internal signal electromigration.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014
Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs.
Proceedings of the 19th IEEE European Test Symposium, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
Proceedings of the 2014 International 3D Systems Integration Conference, 2014
2013
ACM Trans. Design Autom. Electr. Syst., 2013
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
Using electromagnetic emanations for variability characterization in Flash-based FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Simultaneous gate sizing and Vth assignment using Lagrangian Relaxation and delay sensitivities.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013
Simultaneous gate sizing and Vt assignment using Fanin/Fanout ratio and Simulated Annealing.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Instruction-driven timing CPU model for efficient embedded software development using OVP.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Combining fault tolerance and serialization effort to improve yield in 3D Networks-on-Chip.
Proceedings of the 20th IEEE International Conference on Electronics, 2013
System-level thermal modeling for 3D circuits: Characterization with a 65nm memory-on-logic circuit.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
Transistor sizing and gate sizing using geometric programming considering delay minimization.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the 13th Latin American Test Workshop, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Efficient area and power multiplication part of FFT based on twiddle factor decomposition.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
IEEE Trans. Ind. Electron., 2011
Proceedings of the 24th Symposium on Integrated Circuits and Systems Design, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
Asynchronous circuits as alternative for mitigation of long-duration transient faults in deep-submicron technologies.
Microelectron. Reliab., 2010
Low-sensitivity to process variations aging sensor for automotive safety-critical applications.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 11th Latin American Test Workshop, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Design and verification of a layer-2 Ethernet MAC classification engine for a Gigabit Ethernet switch.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
The Fidelity Property of the Elmore Delay Model in actual comparison of routing algorithms.
Proceedings of the 28th International Conference on Computer Design, 2010
Proceedings of the 47th Design Automation Conference, 2010
2009
IEEE Trans. Very Large Scale Integr. Syst., 2009
Challenges and Emerging Technologies for System Integration beyond the End of the Roadmap of Nano-CMOS.
Proceedings of the VLSI-SoC: Technologies for Systems Integration, 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009
Proceedings of the 10th Latin American Test Workshop, 2009
Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies.
Proceedings of the 10th Latin American Test Workshop, 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
An automated design methodology for layout generation targeting power leakage minimization.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
An On-board Data-Handling Computer for Deep-Space Exploration Built Using Commercial-Off-the-Shelf SRAM-Based FPGAs.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009
A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Ind. Electron., 2007
Técnicas probabilísticas para análise de yield em nível elétrico usando propagação de erros e derivadas numéricas.
RITA, 2007
A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis.
J. Electron. Test., 2007
Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC.
Des. Autom. Embed. Syst., 2007
Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC.
Proceedings of the 10th International Workshop on Software and Compilers for Embedded Systems, 2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the 2007 International Symposium on Physical Design, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates.
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Considering Zero-Arrival Time and Block-Arrival Time in Hierarchical Functional Timing Analysis.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Unbalacing the I/O Pins Partitioning for Minimizing Inter-Tier Vias in 3D VLSI Circuits.
Proceedings of the 13th IEEE International Conference on Electronics, 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Desenvolvimento de Técnicas de Tolerância à Falhas para Componentes Programáveis por SRAM.
RITA, 2005
An Automatic Technique for Optimizing Reed-Solomon Codes to Improve Fault Tolerance in Memories.
IEEE Des. Test Comput., 2005
A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Designing Low-Power Embedded Software for Mass-Produced Microprocessor by Using a Loop Table in On-Chip Memory.
Proceedings of the Integrated Circuit and System Design, 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the New Trends and Technologies in Computer-Aided Learning for Computer-Aided Design, 2005
Proceedings of the From Specification to Embedded Systems Application [International Embedded Systems Symposium, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
RITA, 2004
IEEE Des. Test Comput., 2004
Lookup-based Remote Laboratory for FPGA Digital Design Prototyping.
Proceedings of the e-learning and Virtual and Remote Laboratories, 2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004
A New Transistor Folding Algorithm Applied to an Automatic Full-Custom Layout Generation Tool.
Proceedings of the Integrated Circuit and System Design, 2004
Requirements for Computer-Aided Learning from the Point of View of Electronic Design.
Proceedings of the EDUTECH, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the First Conference on Computing Frontiers, 2004
Proceedings of the First Conference on Computing Frontiers, 2004
2003
ACM Trans. Design Autom. Electr. Syst., 2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
Proceedings of the VLSI-SOC: From Systems to Chips, 2003
A New Macro-cell Generation Strategy for three metal layer CMOS Technologies.
Proceedings of the IFIP VLSI-SoC 2003, 2003
A study on the performance of fast initial placement algorithms.
Proceedings of the IFIP VLSI-SoC 2003, 2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations.
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Proceedings of the 16th Annual Symposium on Integrated Circuits and Systems Design, 2003
Proceedings of the Integrated Circuit and System Design, 2003
Reducing Authoring Costs of Online Training in Microelectronics Design by Reusing Design Documentation Content.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003
Supporting Consistency Control between Functional and Structural Views in Interface-based Design Models.
Proceedings of the Forum on specification and Design Languages, 2003
Proceedings of the 2003 Design, 2003
Ubiquitous Access to Reconfigurable Hardware: Application Scenarios and Implementation Issues.
Proceedings of the 2003 Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
2002
Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
Analyzing Area and Performance Penalty of Protecting Different Digital Modules with Hamming Code and Triple Modular Redundancy.
Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002
A Comparison Between Testability Measures Applied to Complex Gates.
Proceedings of the 3rd Latin American Test Workshop, 2002
Injecting Multiple Upsets in a SEU tolerant 8051 Micro-controller.
Proceedings of the 3rd Latin American Test Workshop, 2002
Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002
Computing: The Shape of an Evolving Discipline.
Proceedings of the Informatics Curricula and Teaching Methods, 2002
Comparative Analysis and Application of Data Repository Infrastructure for Collaboration-Enabled Distributed Design Environments.
Proceedings of the 2002 Design, 2002
2001
Análise de Timing Funcional de Circuitos VLSI Contendo Portas Complexas.
RITA, 2001
Future Gener. Comput. Syst., 2001
J. Electron. Test., 2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
Proceedings of the 14th Annual Symposium on Integrated Circuits and Systems Design, 2001
A Timed Calculus for ATG-Based Timing Analysis with Complex Gates.
Proceedings of the 2nd Latin American Test Workshop, 2001
Distributed Collaborative Design over Cave2 Framework.
Proceedings of the SOC Design Methodologies, 2001
2000
Specification and design of an Ethernet Interface soft IP.
J. Braz. Comput. Soc., 2000
Proceedings of the Advances in Artificial Intelligence, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the Computer-Assisted Information Retrieval (Recherche d'Information et ses Applications), 2000
A Self-Testing Mask Programmable Matrix Using Built-in Current Sensing.
Proceedings of the 1st Latin American Test Workshop, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 1999
Designing a Mask Programmable Matrix for Sequential Circuits.
Proceedings of the VLSI: Systems on a Chip, 1999
1998
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998
Proceedings of the 11th Annual Symposium on Integrated Circuits Design, 1998