Ricardo A. L. Reis
Orcid: 0000-0001-5781-5858
According to our database1,
Ricardo A. L. Reis
authored at least 28 papers
between 2004 and 2021.
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Bibliography
2021
Voltage Scaling Influence on the Soft Error Susceptibility of a FinFET-based Circuit.
Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021
Sensitivity of FinFET Adders to PVT Variations and Sleep Transistor as a Mitigation Strategy.
Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2021
2020
Proceedings of the IEEE Latin-American Test Symposium, 2020
Hardware Architecture for the Regular Interpolation Filter of the AV1 Video Coding Standard.
Proceedings of the 28th European Signal Processing Conference, 2020
2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the VLSI-SoC: New Technology Enabler, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019
Cryptography by Synchronization of Hopfield Neural Networks that Simulate Chaotic Signals Generated by the Human Body.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
2017
Radiation sensitivity of XOR topologies in multigate technologies under voltage variability.
Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017
Temperature dependence and ZTC bias point evaluation of sub 20nm bulk multigate devices.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
SET response of FinFET-based majority voter circuits under work-function fluctuation.
Proceedings of the 24th IEEE International Conference on Electronics, Circuits and Systems, 2017
2016
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
2015
Proceedings of the System Level Design from HW/SW to Memory for Embedded Systems, 2015
2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2007
Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
2006
Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
2004
Proceedings of the 17th Annual Symposium on Integrated Circuits and Systems Design, 2004