Rezgar Sadeghi

According to our database, Rezgar Sadeghi authored at least 11 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

AZMA: A Zynq-Based Monitoring and Fault Injection Framework for Processor Assessment.

Zahra Mahdavi, Rezgar Sadeghi, Ali Shayanpour, Amirhosein Yazdanpanah, Zainalabedin Navabi

Proceedings of the IEEE East-West Design & Test Symposium, 2024

Configurable DRAM Access for Neural Network Accelerators: A SystemC Virtual Platform Approach.

Tina Hashemi, Rezgar Sadeghi, Maryam Rajabalipanah, Zahra Hojati, Zainalabedin Navabi

Proceedings of the IEEE East-West Design & Test Symposium, 2024

Real-Time Automotive Accident Detection Using Unsupervised Machine Learning.

Reza Baharvand, Mahsa Jamshidi, Mozhgan Rezaie Manavand, Rezgar Sadeghi, Zainalabedin Navabi

Proceedings of the IEEE East-West Design & Test Symposium, 2024

2022

On-Chip Training of Crosstalk Predictors to Fit Uncertainties.

Rezgar Sadeghi, Ehsan Akbari, Mohamad Ali Saber

Proceedings of the IEEE European Test Symposium, 2022

2020

LUT Input Reordering to Reduce Aging Impact on FPGA LUTs.

Mohammad Ebrahimi, Rezgar Sadeghi, Zainalabedin Navabi

IEEE Trans. Computers, 2020

ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links.

Katayoon Basharkhah, Rezgar Sadeghi, Nooshin Nosrati, Zainalabedin Navabi

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Built-In Predictors for Dynamic Crosstalk Avoidance.

Rezgar Sadeghi, Zainalabedin Navabi

Proceedings of the IEEE European Test Symposium, 2020

2019

An ESL Environment for Modeling Electrical Interconnect Faults.

Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi

Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.

Saba Yousefzadeh, Katayoon Basharkhah, Nooshin Nosrati, Rezgar Sadeghi, Jaan Raik, Maksim Jenihhin, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment.

Nooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Carna Zivkovic, Christoph Grimm, Zainalabedin Navabi

Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling.

Rezgar Sadeghi, Nooshin Nosrati, Katayoon Basharkhah, Zainalabedin Navabi

Proceedings of the 24th IEEE European Test Symposium, 2019