Rezgar Sadeghi

According to our database1, Rezgar Sadeghi authored at least 11 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
AZMA: A Zynq-Based Monitoring and Fault Injection Framework for Processor Assessment.
Proceedings of the IEEE East-West Design & Test Symposium, 2024

Configurable DRAM Access for Neural Network Accelerators: A SystemC Virtual Platform Approach.
Proceedings of the IEEE East-West Design & Test Symposium, 2024

Real-Time Automotive Accident Detection Using Unsupervised Machine Learning.
Proceedings of the IEEE East-West Design & Test Symposium, 2024

2022
On-Chip Training of Crosstalk Predictors to Fit Uncertainties.
Proceedings of the IEEE European Test Symposium, 2022

2020
LUT Input Reordering to Reduce Aging Impact on FPGA LUTs.
IEEE Trans. Computers, 2020

ESL, Back-annotating Crosstalk Fault Models into High-level Communication Links.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Built-In Predictors for Dynamic Crosstalk Avoidance.
Proceedings of the IEEE European Test Symposium, 2020

2019
An ESL Environment for Modeling Electrical Interconnect Faults.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019

An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019

Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling.
Proceedings of the 24th IEEE European Test Symposium, 2019


  Loading...