Rezgar Sadeghi
According to our database1,
Rezgar Sadeghi
authored at least 11 papers
between 2019 and 2024.
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Bibliography
2024
AZMA: A Zynq-Based Monitoring and Fault Injection Framework for Processor Assessment.
Proceedings of the IEEE East-West Design & Test Symposium, 2024
Configurable DRAM Access for Neural Network Accelerators: A SystemC Virtual Platform Approach.
Proceedings of the IEEE East-West Design & Test Symposium, 2024
Proceedings of the IEEE East-West Design & Test Symposium, 2024
2022
Proceedings of the IEEE European Test Symposium, 2022
2020
IEEE Trans. Computers, 2020
Proceedings of the 38th IEEE VLSI Test Symposium, 2020
Proceedings of the IEEE European Test Symposium, 2020
2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
An Accelerator-based Architecture Utilizing an Efficient Memory Link for Modern Computational Requirements.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019
Making System Level Test Possible by a Mixed-mode, Multi-level, Integrated Modeling Environment.
Proceedings of the 2019 IEEE East-West Design & Test Symposium, 2019
Back-annotation of Interconnect Physical Properties for System-Level Crosstalk Modeling.
Proceedings of the 24th IEEE European Test Symposium, 2019