Reza Sabbaghi-Nadooshan

Orcid: 0000-0003-1201-914X

According to our database1, Reza Sabbaghi-Nadooshan authored at least 35 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A QTCP/IP reference model for partially trusted-node-based quantum-key-distribution-secured optical networks.
Quantum Inf. Process., March, 2024

A fault-tolerant and energy-efficient design of RAM cell and PIM structure in quantum technology.
Sustain. Comput. Informatics Syst., 2024

Design of ternary reversible Feynman and Toffoli gates in ternary quantum-dot cellular automata.
Nano Commun. Networks, 2024

2023
A 3D Tensor Representation of Speech and 3D Convolutional Neural Network for Emotion Recognition.
Circuits Syst. Signal Process., July, 2023

Tree router design using a novel optimal QCA DEMUX.
Nano Commun. Networks, March, 2023

Deep Convolutional Neural Network and Gray Wolf Optimization Algorithm for Speech Emotion Recognition.
Circuits Syst. Signal Process., 2023

2022
Novel ternary adders and subtractors in quantum cellular automata.
J. Supercomput., 2022

Realization of processing-in-memory using binary and ternary quantum-dot cellular automata.
J. Supercomput., 2022

All-optical half adder based on triangular lattice photonic crystals with uniform structural parameters.
Photonic Netw. Commun., 2022

Novel Fault-Tolerant Processing in Memory Cell in Ternary Quantum-Dot Cellular Automata.
J. Electron. Test., 2022

Toward Quaternary QCA: Novel Majority and XOR Fuzzy Gates.
IEEE Access, 2022

2021
Investigating multiple defects on a new fault-tolerant three-input QCA majority gate.
J. Supercomput., 2021

A creative concept for designing and simulating quaternary logic gates in quantum-dot cellular automata.
Frontiers Inf. Technol. Electron. Eng., 2021

New polarization and power calculations with error elimination in ternary QCA.
Comput. Electr. Eng., 2021

2018
Innovative model for ternary QCA gates.
IET Circuits Devices Syst., 2018

Designing ternary quantum-dot cellular automata logic circuits based upon an alternative model.
Comput. Electr. Eng., 2018

Accurate Performance Bounds Calculation for Dynamic Voltage-Freq Islands in Best Effort NoCs.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2016
A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Optimization of quantum networks using novel non-blocking optical switches.
Opt. Switch. Netw., 2016

Design of New QCA LFSR and NLFSR for Grain-128 Stream Cipher.
J. Circuits Syst. Comput., 2016

An efficient on-chip network with packet compression capability.
Proceedings of the International SoC Design Conference, 2016

2015
Analytical performance modeling of de Bruijn inspired mesh-based network-on-chips.
Microprocess. Microsystems, 2015

2014
A conventional design and simulation for CLB implementation of an FPGA quantum-dot cellular automata.
Microprocess. Microsystems, 2014

A novel design of 8-bit adder/subtractor by quantum-dot cellular automata.
J. Comput. Syst. Sci., 2014

2013
Analytical performance modeling of shuffle-exchange inspired mesh-based Network-on-Chips.
Perform. Evaluation, 2013

Sphere-based topology for networks-on-chip.
Int. J. Embed. Syst., 2013

2012
The 2D digraph-based NoCs: attractive alternatives to the 2D mesh NoCs.
J. Supercomput., 2012

A conventional design for CLB implementation of a FPGA in quantum-dot cellular automata (QCA).
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

2011
A Novel Elliptic curve cryptography Processor using NoC design
CoRR, 2011

Using Genetic Algorithm in the Evolutionary Design of Sequential Logic Circuits
CoRR, 2011

Square topology: A novel topology for NoCs.
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011

2010
The 2D SEM: A novel high-performance and low-power mesh-based topology for networks-on-chip.
Int. J. Parallel Emergent Distributed Syst., 2010

2008
The Shuffle-Exchange Mesh Topology for 3D NoCs.
Proceedings of the 9th International Symposium on Parallel Architectures, 2008

A novel high-performance and low-power mesh-based NoC.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

The 2D DBM: An attractive alternative to the simple 2D mesh topology for on-chip networks.
Proceedings of the 26th International Conference on Computer Design, 2008


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