Reza M. Rad

According to our database1, Reza M. Rad authored at least 17 papers between 2006 and 2012.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2012
Bit string analysis of Physical Unclonable Functions based on resistance variations in metals and transistors.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

2011
An Experimental Analysis of Power and Delay Signal-to-Noise Requirements for Detecting Trojans and Methods for Achieving the Required Detection Sensitivities.
IEEE Trans. Inf. Forensics Secur., 2011

REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

2010
A Sensitivity Analysis of Power Signal Methods for Detecting Hardware Trojans Under Real Process and Environmental Conditions.
IEEE Trans. Very Large Scale Integr. Syst., 2010

Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad I<sub>DDQ</sub> s.
IEEE Trans. Inf. Forensics Secur., 2010

2009
A Novel Fault Localization Technique Based on Deconvolution and Calibration of Power Pad Transients Signals.
J. Electron. Test., 2009

2008
SCT: A novel approach for testing and configuring nanoscale devices.
ACM J. Emerg. Technol. Comput. Syst., 2008

Defect Tolerance for Nanoscale Crossbar-Based Devices.
IEEE Des. Test Comput., 2008

Power supply signal calibration techniques for improving detection resolution to hardware Trojans.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Sensitivity Analysis to Hardware Trojans using Power Supply Transient Signals.
Proceedings of the IEEE International Workshop on Hardware-Oriented Security and Trust, 2008

2007
Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing.
ACM J. Emerg. Technol. Comput. Syst., 2007

2006
SCT: An Approach For Testing and Configuring Nanoscale Devices.
Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Test and recovery for fine-grained nanoscale architectures.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

Fine-grained island style architecture for molecular electronic devices.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

A new hybrid FPGA with nanoscale clusters and CMOS routing.
Proceedings of the 43rd Design Automation Conference, 2006


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