Reza Inanlou

Orcid: 0000-0003-2630-876X

According to our database1, Reza Inanlou authored at least 6 papers between 2014 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2022
Algorithm Level Error Detection in Low Voltage Systolic Array.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2020
An asynchronous pulse width modulator for DC-DC buck converter.
Int. J. Circuit Theory Appl., 2020

Arithmetic Tracking Adaptive SAR ADC for Signals With Low-Activity Periods.
IEEE Access, 2020

2019
A Reconfigurable Dual-Mode Tracking SAR ADC without Analog Subtraction.
Proceedings of the Signal Processing: Algorithms, 2019

2018
ADC-Assisted Random Sampler Architecture for Efficient Sparse Signal Acquisition.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2014
A 10-Bit 0.5 V 100 KS/S SAR ADC with a New rail-to-rail Comparator for Energy Limited Applications.
J. Circuits Syst. Comput., 2014


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