Reza Hojabr

According to our database, Reza Hojabr authored at least 15 papers between 2015 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

X-cache: a modular architecture for domain-specific caches.

Ali Sedaghati, Milad Hakimi, Reza Hojabr, Arrvindh Shriraman

Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022

mu-grind: A Framework for Dynamically Instrumenting HLS-Generated RTL.

Parmida Vahdatniya, Amirali Sharifian, Reza Hojabr, Arrvindh Shriraman

Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2022

2021

High-Performance Deterministic Stochastic Computing Using Residue Number System.

Kamyar Givaki, Reza Hojabr, MohammadHosein Gholamrezaei, Ahmad Khonsari, Saeid Gorgin, Dara Rahmati, M. Hassan Najafi

IEEE Des. Test, 2021

Real-Time Hamilton-Jacobi Reachability Analysis of Autonomous System With An FPGA.

Minh Bui, Michael Lu, Reza Hojabr, Mo Chen, Arrvindh Shriraman

Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021

SPAGHETTI: Streaming Accelerators for Highly Sparse GEMM on FPGAs.

Reza Hojabr, Ali Sedaghati, Amirali Sharifian, Ahmad Khonsari, Arrvindh Shriraman

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

X-Layer: Building Composable Pipelined Dataflows for Low-Rank Convolutions.

Naveen Vedula, Reza Hojabr, Ahmad Khonsari, Arrvindh Shriraman

Proceedings of the 30th International Conference on Parallel Architectures and Compilation Techniques, 2021

2020

Real-Time Formal Verification of Autonomous Systems With An FPGA.

Minh Bui, Michael Lu, Reza Hojabr, Mo Chen, Arrvindh Shriraman

CoRR, 2020

On the Resilience of Deep Learning for Reduced-voltage FPGAs.

Kamyar Givaki, Behzad Salami, Reza Hojabr, S. M. Reza Tayaranian, Ahmad Khonsari, Dara Rahmati, Saeid Gorgin, Adrián Cristal, Osman S. Unsal

Proceedings of the 28th Euromicro International Conference on Parallel, 2020

TaxoNN: A Light-Weight Accelerator for Deep Neural Network Training.

Reza Hojabr, Kamyar Givaki, Kossar Pourahmadi, Parsa Nooralinejad, Ahmad Khonsari, Dara Rahmati, M. Hassan Najafi

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2019

μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators.

Amirali Sharifian, Reza Hojabr, Navid Rahimi, Sihao Liu, Apala Guha, Tony Nowatzki, Arrvindh Shriraman

Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

SkippyNN: An Embedded Stochastic-Computing Accelerator for Convolutional Neural Networks.

Reza Hojabr, Kamyar Givaki, S. M. Reza Tayaranian, Parsa Esfahanian, Ahmad Khonsari, Dara Rahmati, M. Hassan Najafi

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Using Residue Number Systems to Accelerate Deterministic Bit-stream Multiplication.

Kamyar Givaki, Reza Hojabr, M. Hassan Najafi, Ahmad Khonsari, M. Hossein Gholamrezayi, Saeid Gorgin, Dara Rahmati

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2017

Customizing Clos Network-on-Chip for Neural Networks.

Reza Hojabr, Mehdi Modarressi, Masoud Daneshtalab, Ali Yasoubi, Ahmad Khonsari

IEEE Trans. Computers, 2017

Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse.

Ali Yasoubi, Reza Hojabr, Mehdi Modarressi

IEEE Comput. Archit. Lett., 2017

2015

CuPAN - High Throughput On-chip Interconnection for Neural Networks.

Ali Yasoubi, Reza Hojabr, Hengameh Takshi, Mehdi Modarressi, Masoud Daneshtalab

Proceedings of the Neural Information Processing - 22nd International Conference, 2015