Resit Sendag

Orcid: 0000-0002-6922-3363

According to our database1, Resit Sendag authored at least 41 papers between 2001 and 2024.

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Bibliography

2024
NoiseAttack: An Evasive Sample-Specific Multi-Targeted Backdoor Attack Through White Gaussian Noise.
CoRR, 2024

2023
Performance Comparison of Steady State GAs and Generational GAs for Capacitated Vehicle Routing Problems.
Proceedings of the Companion Proceedings of the Conference on Genetic and Evolutionary Computation, 2023

Efficient Implementation of a Genetic Algorithm for the Capacitated Vehicle Routing Problem on a High-Performance FPGA.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
A Multi-GPU Parallel Genetic Algorithm For Large-Scale Vehicle Routing Problems.
Proceedings of the IEEE High Performance Extreme Computing Conference, 2022

2021
Fast Key-Value Lookups with Node Tracker.
ACM Trans. Archit. Code Optim., 2021

2020
Informed Prefetching for Indirect Memory Accesses.
ACM Trans. Archit. Code Optim., 2020

Exploring Prefetching, Pre-Execution and Branch Outcome Streaming for In-Memory Database Lookups.
IEEE Comput. Archit. Lett., 2020

2018
Array Tracking Prefetcher for Indirect Accesses.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

2017
FPGAs versus GPUs in Data centers.
IEEE Micro, 2017

2016
Impact of Future Technologies on Architecture.
IEEE Micro, 2016

Proprietary versus Open Instruction Sets.
IEEE Micro, 2016

2015
Message from the general chair.
Proceedings of the 10th IEEE International Conference on Networking, 2015

2014
An analysis of address and branch patterns with PatternFinder.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

Automatic source code analysis of branch mispredictions.
Proceedings of the 2014 IEEE International Symposium on Workload Characterization, 2014

2013
On the performance and energy-efficiency of multi-core SIMD CPUs and CUDA-enabled GPUs.
Proceedings of the IEEE International Symposium on Workload Characterization, 2013

The impact of data complexity on privacy management in vehicle to infrastructure applications.
Proceedings of the International Conference on Connected Vehicles and Expo, 2013

2012
An FPGA-based multi-core platform for testing and analysis of architectural techniques.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2012

2010
The Future of Architectural Simulation.
IEEE Micro, 2010

Programming Multicores: Do Applications Programmers Need to Write Explicitly Parallel Programs?
IEEE Micro, 2010

An analysis of hard to predict branches.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2010

2009
Adaptive simulation sampling using an Autoregressive framework.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

2008
Low power/area branch prediction using complementary branch predictors.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007
Speed versus Accuracy Trade-Offs in Microarchitectural Simulations.
IEEE Trans. Computers, 2007

Low-Power Design and Temperature Management.
IEEE Micro, 2007

Where Does Security Stand? New Vulnerabilities vs. Trusted Computing.
IEEE Micro, 2007

Reliability: Fallacy or Reality?
IEEE Micro, 2007

Single-Threaded vs. Multithreaded: Where Should We Focus?
IEEE Micro, 2007

The impact of wrong-path memory references in cache-coherent multiprocessor systems.
J. Parallel Distributed Comput., 2007

Branch Misprediction Prediction: Complementary Branch Predictors.
IEEE Comput. Archit. Lett., 2007

2006
Quantifying and reducing the effects of wrong-path memory references in cache-coherent multiprocessor systems.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Evaluating Benchmark Subsetting Approaches.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

2005
The Impact of Incorrectly Speculated Memory Operations in a Multithreaded Architecture.
IEEE Trans. Parallel Distributed Syst., 2005

Multiple-Valued Caches for Power-Efficient Embedded Systems.
Proceedings of the 35th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2005), 2005

Characterizing and Comparing Prevailing Simulation Techniques.
Proceedings of the 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 2005

2004
Improving Data Cache Performance via Address Correlation: An Upper Bound Study.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

2003
Address Correlation: Exceeding the Limits of Locality.
IEEE Comput. Archit. Lett., 2003

Using Incorrect Speculation to Prefetch Data in a Concurrent Multithreaded Processor.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Exploring Memory Access Regularity in Pointer-Intensive Application Programs.
Proceedings of the Intelligent Data Engineering and Automated Learning, 2003

2002
Increasing Instruction-Level Parallelism with Instruction Precomputation (Research Note).
Proceedings of the Euro-Par 2002, 2002

Exploiting the Prefetching Effect Provided by Executing Mispredicted Load Instructions.
Proceedings of the Euro-Par 2002, 2002

2001
Routing and wavelength assignment in optical passive star networks with non-uniform traffic load.
Proceedings of the Global Telecommunications Conference, 2001


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