Reouven Elbaz

According to our database1, Reouven Elbaz authored at least 15 papers between 2005 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
SARFUM: Security Architecture for Remote FPGA Update and Monitoring.
ACM Trans. Reconfigurable Technol. Syst., 2010

Block-Level Added Redundancy Explicit Authentication for Parallelized Encryption and Integrity Checking of Processor-Memory Transactions.
Trans. Comput. Sci., 2010

2009
Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines.
Trans. Comput. Sci., 2009

Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

2008
Secure update Mechanism for Remote Update of FPGA-Based System.
Proceedings of the IEEE Third International Symposium on Industrial Embedded Systems, 2008

Forward-Secure Content Distribution to Reconfigurable Hardware.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

The Reduced Address Space (RAS) for Application Memory Authentication.
Proceedings of the Information Security, 11th International Conference, 2008

Secure FPGA configuration architecture preventing system downgrade.
Proceedings of the FPL 2008, 2008

2007
IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking.
Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

TEC-Tree: A Low-Cost, Parallelizable Tree for Efficient Defense Against Memory Replay Attacks.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2007

2006
Efficient Combination of Data Encryption and Integrity Checking for Embedded Systems.
Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A Comparison of Two Approaches Providing Data Encryption and Authentication on a Processor Memory Bus.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

PE-ICE: Parallelized Encryption and Integrity Checking Engine.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

A parallelized way to provide data encryption and integrity checking on a processor-memory bus.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Hardware Engines for Bus Encryption: A Survey of Existing Techniques.
Proceedings of the 2005 Design, 2005


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