Renshen Wang
According to our database1,
Renshen Wang
authored at least 21 papers
between 2005 and 2023.
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Bibliography
2023
Proceedings of the Document Analysis and Recognition - ICDAR 2023, 2023
FormNetV2: Multimodal Graph Contrastive Learning for Form Document Information Extraction.
Proceedings of the 61st Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2023
2022
Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022
Proceedings of the Document Analysis Systems - 15th IAPR International Workshop, 2022
FormNet: Structural Encoding beyond Sequential Modeling in Form Document Information Extraction.
Proceedings of the 60th Annual Meeting of the Association for Computational Linguistics (Volume 1: Long Papers), 2022
2021
CoRR, 2021
ROPE: Reading Order Equivariant Positional Encoding for Graph-based Document Information Extraction.
Proceedings of the 59th Annual Meeting of the Association for Computational Linguistics and the 11th International Joint Conference on Natural Language Processing, 2021
2012
Scalable hierarchical floorplanning for fast physical prototyping of systems-on-chip.
Proceedings of the International Symposium on Physical Design, 2012
2011
Bus Matrix Synthesis Based on Steiner Graphs for Power Efficient System-on-Chip Communications.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011
2010
PhD thesis, 2010
ACM Trans. Design Autom. Electr. Syst., 2010
Physical synthesis of bus matrix for high bandwidth low power on-chip communications.
Proceedings of the 2010 International Symposium on Physical Design, 2010
2009
Symmetrical buffer placement in clock trees for minimal skew immune to global on-chip variations.
Proceedings of the 27th International Conference on Computer Design, 2009
On the complexity of graph cuboidal dual problems for 3-D floorplanning of integrated circuit design.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.
Proceedings of the 46th Design Automation Conference, 2009
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
2008
Proceedings of the 2008 International Symposium on Physical Design, 2008
Proceedings of the 16th Annual IEEE Symposium on High Performance Interconnects (HOTI 2008), 2008
2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005