Renji Thomas
According to our database1,
Renji Thomas
authored at least 8 papers
between 2010 and 2016.
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Bibliography
2016
Snatch: Opportunistically reassigning power allocation between processor and memory in 3D stacks.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016
EmerGPU: Understanding and mitigating resonance-induced voltage noise in GPU architectures.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
2012
Mitigating the Effects of Process Variation in Ultra-low Voltage Chip Multiprocessors using Dual Supply Voltages and Half-Speed Units.
IEEE Comput. Archit. Lett., 2012
VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012
Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
2011
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011
2010
Proceedings of the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, 2010