René Schüffny
According to our database1,
René Schüffny
authored at least 97 papers
between 1977 and 2020.
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Bibliography
2020
Mean Field Approach for Configuring Population Dynamics on a Biohybrid Neuromorphic System.
J. Signal Process. Syst., 2020
2017
Application-specific architectures for energy-efficient database query processing and optimization.
Microprocess. Microsystems, 2017
CoRR, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Neuromorphic hardware in the loop: Training a deep spiking network on the BrainScaleS wafer-scale system.
Proceedings of the 2017 International Joint Conference on Neural Networks, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits.
IEEE Trans. Biomed. Circuits Syst., 2016
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016
Proceedings of the 53rd Annual Design Automation Conference, 2016
2015
An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS.
IEEE J. Solid State Circuits, 2015
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Bridging the gap between software simulation and emulation on neuromorphic hardware: An investigation of causes, effects and compensation of network-level anomalies in a mixed-signal waferscale neuromorphic modeling platform.
CoRR, 2014
Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS.
CoRR, 2014
CoRR, 2014
A 10 bit 16 MS/s redundant SAR ADC with flexible window function for a digitally controlled DC-DC converter in 28 nm CMOS.
Proceedings of the 2014 NORCHIP, Tampere, Finland, October 27-28, 2014, 2014
10.7 A 105GOPS 36mm<sup>2</sup> heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
VLSI implementation of a conductance-based multi-synapse using switched-capacitor circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Configurable pulse routing architecture for accelerated multi-node neuromorphic systems.
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Neural Schematics as a unified formal graphical representation of large-scale Neural Network Structures.
Frontiers Neuroinformatics, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 International Joint Conference on Neural Networks, 2013
Proceedings of the 20th IEEE International Conference on Electronics, 2013
Live demonstration: Ethernet communication linking two large-scale neuromorphic systems.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
Behavioral model of a continuous current integrator with time discrete feedback and sampling.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
Accuracy evaluation of numerical methods used in state-of-the-art simulators for spiking neural networks.
J. Comput. Neurosci., 2012
On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links.
Int. J. Embed. Real Time Commun. Syst., 2012
Developing structural constraints on connectivity for biologically embedded neural networks.
Biol. Cybern., 2012
Proceedings of the Advances in Neural Information Processing Systems 25: 26th Annual Conference on Neural Information Processing Systems 2012. Proceedings of a meeting held December 3-6, 2012
A 335Mb/s 3.9mm<sup>2</sup> 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Dedicated FPGA communication architecture and design for a large-scale neuromorphic system.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
Analyzing the Scaling of Connectivity in Neuromorphic Hardware and in Models of Neural Networks.
IEEE Trans. Neural Networks, 2011
A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems.
Biol. Cybern., 2011
Proceedings of the 2011 NORCHIP, Lund, Sweden, November 14-15, 2011, 2011
Proceedings of the 2011 International Symposium on System on Chip, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput.
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 18th European Symposium on Artificial Neural Networks, 2010
GMPath - A Path Language for Navigation, Information Query and Modification of Data Graphs.
Proceedings of the Artificial Neural Networks and Intelligent Information Processing, 2010
A Software Framework for Mapping Neural Networks to a Wafer-scale Neuromorphic Hardware System.
Proceedings of the Artificial Neural Networks and Intelligent Information Processing, 2010
2009
Microelectron. J., 2009
Neurocomputing, 2009
On the Relation between Bursts and Dynamic Synapse Properties: A Modulation-Based Ansatz.
Comput. Intell. Neurosci., 2009
A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 17th European Symposium on Artificial Neural Networks, 2009
2008
Proceedings of the Advances in Neuro-Information Processing, 15th International Conference, 2008
2007
IEEE Trans. Neural Networks, 2007
Proceedings of the 7th International Conference on Hybrid Intelligent Systems, 2007
2005
2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004
Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation.
Proceedings of the Image Processing: Algorithms and Systems III, 2004
Proceedings of the ARCS 2004, 2004
2003
IEEE J. Solid State Circuits, 2003
On-chip digital noise reduction for integrated CMOS Cameras.
Proceedings of the Visual Communications and Image Processing 2003, 2003
Proceedings of the Seventh International Symposium on Signal Processing and Its Applications, 2003
Comparison of accumulation units for analog realizations of a path searcher for a UMTS receiver.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
Proceedings of the Seventh International Conference on Digital Image Computing: Techniques and Applications, 2003
Proceedings of the Seventh International Conference on Digital Image Computing: Techniques and Applications, 2003
2002
Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity.
Proceedings of the 12th IEEE Workshop on Neural Networks for Signal Processing, 2002
An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights.
Proceedings of the Artificial Neural Networks, 2002
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002
2001
A vision device for image processing.
Proceedings of the Signal and Image Processing (SIP 2001), 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
2000
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
1999
Proceedings of the Third International Conference on Knowledge-Based Intelligent Information Engineering Systems, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1996
An Architectural Study of a Massively Parallel Processor for Convolution-Type Operations in Complex Vision Tasks.
Proceedings of the Artificial Neural Networks, 1996
1977
Untersuchungen zur Gunn-Elektronik unter besonderer Berücksichtigung der numerischen Analyse.
PhD thesis, 1977