Renaud Pacalet

According to our database, Renaud Pacalet authored at least 55 papers between 1997 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Masked Vector Sampling for HQC.

Maxime Spyropoulos, David Vigilant, Fabrice Perion, Renaud Pacalet, Laurent Sauvage

IACR Cryptol. ePrint Arch., 2024

2023

Execution trace analysis for a precise understanding of latency violations.

Maysam Zoor, Ludovic Apvrille, Renaud Pacalet, Sophie Coudert

Softw. Syst. Model., October, 2023

2021

Multi-resource scheduling for FPGA systems.

Matteo Bertolino, Renaud Pacalet, Ludovic Apvrille, Andrea Enrici

Microprocess. Microsystems, November, 2021

Execution Trace Analysis for a Precise Understanding of Latency Violations.

Maysam Zoor, Ludovic Apvrille, Renaud Pacalet

Proceedings of the 24th International Conference on Model Driven Engineering Languages and Systems, 2021

2020

Impact of Security Measures on Performance Aspects in SysML Models.

Maysam Zoor, Ludovic Apvrille, Renaud Pacalet

Proceedings of the 8th International Conference on Model-Driven Engineering and Software Development, 2020

SysML models: studying safety and security measures impact on performance using graph tainting.

Maysam Zoor, Ludovic Apvrille, Renaud Pacalet

Proceedings of the MODELS '20: ACM/IEEE 23rd International Conference on Model Driven Engineering Languages and Systems, 2020

Design Space Exploration with Deterministic Latency Guarantees for Crossbar MPSoC Architectures.

Bogdan Uscumlic, Andrea Enrici, Renaud Pacalet, Amna Gharbi, Ludovic Apvrille, Lionel Natarianni, Laurent Roullet

Proceedings of the 2020 IEEE International Conference on Communications, 2020

Efficient and Exact Design Space Exploration for Heterogeneous and Multi-Bus Platforms.

Amna Gharbi, Andrea Enrici, Bogdan Uscumlic, Ludovic Apvrille, Renaud Pacalet

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Efficient Scheduling of FPGAs for Cloud Data Center Infrastructures.

Matteo Bertolino, Renaud Pacalet, Ludovic Apvrille, Andrea Enrici

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

2019

Dynamic Guest Memory Resizing - Paravirtualized Approach.

Maciej Bielski, Alvise Rigo, Renaud Pacalet

Proceedings of the 27th Euromicro International Conference on Parallel, 2019

Static Data-Flow Analysis of UML/SysML Functional Views for Signal and Image Processing Applications.

Andrea Enrici, Ludovic Apvrille, Renaud Pacalet, Minh Hiep Pham

Proceedings of the Model-Driven Engineering and Software Development, 2019

Efficient Data-Flow Analysis of UML/SysML Diagrams for Optimized Model Compilation of Hardware-software Systems.

Andrea Enrici, Ludovic Apvrille, Renaud Pacalet

Proceedings of the 7th International Conference on Model-Driven Engineering and Software Development, 2019

Modeling the Trade-off Between Security and Performance to Support the Product Life Cycle.

Radek Fujdiak, Petr Blazek, Ludovic Apvrille, Zdenek Martinasek, Petr Mlynek, Renaud Pacalet, David Smekal, Pavel Mrnustik, Maros Barabas, Maysam Zoor

Proceedings of the 8th Mediterranean Conference on Embedded Computing, 2019

Odyn: Deadlock Prevention and Hybrid Scheduling Algorithm for Real-Time Dataflow Applications.

Benjamin Dauphin, Renaud Pacalet, Andrea Enrici, Ludovic Apvrille

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018

Model-Based Programming for Multi-processor Platforms with TTool/DIPLODOCUS and OMC.

Andrea Enrici, Julien Lallet, Renaud Pacalet, Ludovic Apvrille, Karol Desnos, Imran Latif

Proceedings of the Model-Driven Engineering and Software Development, 2018

A Model Compilation Approach for Optimized Implementations of Signal-processing Systems.

Andrea Enrici, Julien Lallet, Imran Latif, Ludovic Apvrille, Renaud Pacalet, Adrien Canuel

Proceedings of the 6th International Conference on Model-Driven Engineering and Software Development, 2018

2017

A Model-Driven Engineering Methodology to Design Parallel and Distributed Embedded Systems.

Andrea Enrici, Ludovic Apvrille, Renaud Pacalet

ACM Trans. Design Autom. Electr. Syst., 2017

2016

Survey on Memory and Devices Disaggregation Solutions for HPC Systems.

Maciej Bielski, Christian Pinto, Daniel Raho, Renaud Pacalet

Proceedings of the 2016 IEEE Intl Conference on Computational Science and Engineering, 2016

2015

Performance optimizations of integrity checking based on Merkle trees.

Salaheddine Ouaarab, Guillaume Duc, Renaud Pacalet

Proceedings of the Fourth Workshop on Hardware and Architectural Support for Security and Privacy, 2015

Hardware-assisted Memory Tracing on New SoCs Embedding FPGA Fabrics.

Letitia W. Li, Guillaume Duc, Renaud Pacalet

Proceedings of the 31st Annual Computer Security Applications Conference, 2015

2014

A UML Model-Driven Approach to Efficiently Allocate Complex Communication Schemes.

Andrea Enrici, Ludovic Apvrille, Renaud Pacalet

Proceedings of the Model-Driven Engineering Languages and Systems, 2014

SecBus, a Software/Hardware Architecture for Securing External Memories.

Jeremie Brunel, Renaud Pacalet, Salaheddine Ouaarab, Guillaume Duc

Proceedings of the 2nd IEEE International Conference on Mobile Cloud Computing, 2014

Model-Driven Design of Software Defined Radio Applications Based on UML.

Jair Gonzalez-Pina, Renaud Pacalet

Proceedings of the Embedded Systems Development, From Functional Models to Implementations, 2014

2013

Formal system-level design space exploration.

Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet

Concurr. Comput. Pract. Exp., 2013

TRESCCA - Trustworthy Embedded Systems for Secure Cloud Computing.

Gunnar Schomaker, Andreas Herrholz, Guillaume Duc, Renaud Pacalet, Salvatore Raho, Miltos D. Grammatikakis, Marcello Coppola, Ignacio Garcia Vega

Proceedings of the 2013 International Conference on Availability, Reliability and Security, 2013

2012

Dynamic Power Management for the Iterative Decoding of Turbo Codes.

Erick Amador, Raymond Knopp, Renaud Pacalet, Vincent Rezard

IEEE Trans. Very Large Scale Integr. Syst., 2012

DiplodocusDF, a Domain-Specific Modelling Language for Software Defined Radio Applications.

Jair Gonzalez-Pina, Rabéa Ameur-Boulifa, Renaud Pacalet

Proceedings of the 38th Euromicro Conference on Software Engineering and Advanced Applications, 2012

Flexible front-end processing for software defined radio applications using application specific instruction-set processors.

Carina Schmidt-Knorreck, Renaud Pacalet, Andreas Minwegen, Uwe Deidersen, Torsten Kempf, Raymond Knopp, Gerd Ascheid

Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012

2010

Evaluation of Power Constant Dual-Rail Logics Countermeasures against DPA with Design Time Security Metrics.

Sylvain Guilley, Laurent Sauvage, Florent Flament, Vinh-Nga Vong, Philippe Hoogvorst, Renaud Pacalet

IEEE Trans. Computers, 2010

Dynamic Power Management on LDPC Decoders.

Erick Amador, Raymond Knopp, Vincent Rezard, Renaud Pacalet

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Architectures for cognitive radio testbeds and demonstrators - An overview.

Oscar Gustafsson, Kiarash Amiri, Dennis Andersson, Anton Blad, Christian Bonnet, Joseph R. Cavallaro, Jeroen Declerck, Antoine Dejonghe, Patrik Eliardsson, Miguel Glassee, Aawatif Hayar, Lieven Hollevoet, Christopher Hunter, Madhura Joshi, Florian Kaltenberger, Raymond Knopp, Khanh Le, Zoran Miljanic, Patrick Murphy, Frederik Naessens, Navid Nikaein, Dominique Nussbaum, Renaud Pacalet, Praveen Raghavan, Ashutosh Sabharwal, Onkar Sarode, Predrag Spasojevic, Yang Sun, Hugo M. Tullberg, Tom Vander Aa, Liesbet Van der Perre, Michelle Wetterwald, Michael Wu

Proceedings of the 5th International ICST Conference on Cognitive Radio Oriented Wireless Networks and Communications, 2010

2009

Fast Simulation Techniques for Design Space Exploration.

Daniel Knorreck, Ludovic Apvrille, Renaud Pacalet

Proceedings of the Objects, Components, Models and Patterns, 47th International Conference, 2009

High-Level System Modeling for Rapid HW/SW Architecture Exploration.

Chafic Jaber, Andreas Kanstein, Ludovic Apvrille, Amer Baghdadi, Patricia Le Moenner, Renaud Pacalet

Proceedings of the Twentienth IEEE/IFIP International Symposium on Rapid System Prototyping, 2009

Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques.

Dominique Nussbaum, Karim Khalfallah, Christophe Moy, Amor Nafkha, Pierre Leray, Julien Delorme, Jacques Palicot, Jérôme Martin, Fabien Clermidy, Bertrand Mercier, Renaud Pacalet

Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

SecBus: Operating System controlled hierarchical page-based memory bus protection.

Lifeng Su, Stephan Courcambeck, Pierre Guillemin, Christian Schwarz, Renaud Pacalet

Proceedings of the Design, Automation and Test in Europe, 2009

Optimum LDPC decoder: a memory architecture problem.

Erick Amador, Renaud Pacalet, Vincent Rezard

Proceedings of the 46th Design Automation Conference, 2009

2008

Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks.

Sylvain Guilley, Laurent Sauvage, Philippe Hoogvorst, Renaud Pacalet, Guido Marco Bertoni, Sumanta Chaudhuri

IEEE Trans. Computers, 2008

Evaluation of ASIPs Design with LISATek.

Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet

Proceedings of the Embedded Computer Systems: Architectures, 2008

Silicon-level Solutions to Counteract Passive and Active Attacks.

Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Nidhal Selmane, Renaud Pacalet

Proceedings of the Fifth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2008

Flexible Baseband Architectures for Future Wireless Systems.

Muhammad Najam-ul-Islam, Rizwan Rasheed, Renaud Pacalet, Raymond Knopp, Karim Khalfallah

Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008

Application Specific Processors for Multimedia Applications.

Muhammad Rashid, Ludovic Apvrille, Renaud Pacalet

Proceedings of the 11th IEEE International Conference on Computational Science and Engineering, 2008

2007

A fast pipelined multi-mode DES architecture operating in IP representation.

Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet

Integr., 2007

Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors.

Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu

IEEE Des. Test Comput., 2007

Reconfigurable DSP Architectures for SDR Applications.

Muhammad Najam-ul-Islam, Karim Khalfallah, Raymond Knopp, Renaud Pacalet

Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006

Un environnement de conception de systèmes distribués basé sur UML.

Ludovic Apvrille, Pierre de Saqui-Sannes, Renaud Pacalet, Axelle Apvrille

Ann. des Télécommunications, 2006

A UML-based Environment for System Design Space Exploration.

Ludovic Apvrille, Muhammad Waseem, Rabéa Ameur-Boulifa, Sophie Coudert, Renaud Pacalet

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Using GPU for fast Block-Matching.

Sebastien Mazare, Jean-Luc Dugelay, Renaud Pacalet

Proceedings of the 14th European Signal Processing Conference, 2006

Abstract Application Modeling for System Design Space Exploration.

Muhammad Waseem, Ludovic Apvrille, Rabéa Ameur-Boulifa, Sophie Coudert, Renaud Pacalet

Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005

The "Backend Duplication" Method.

Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004

SoCs security: a war against side-channels.

Sylvain Guilley, Renaud Pacalet

Ann. des Télécommunications, 2004

CMOS Structures Suitable for Secured Hardware.

Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost

Proceedings of the 2004 Design, 2004

Differential Power Analysis Model and Some Results.

Sylvain Guilley, Philippe Hoogvorst, Renaud Pacalet

Proceedings of the Smart Card Research and Advanced Applications VI, 2004

2000

LUX: A Heterogeneous Parallel Computer Dedicated to Ray Tracing.

Stéphane Mancini, Renaud Pacalet

Parallel Distributed Comput. Pract., 2000

1999

LUX: An Heterogeneous Function Composition Parallel Computer for Graphics.

Stéphane Mancini, Renaud Pacalet

Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999

1997

A VLSI Architecture for Image Geometrical Transformations Using an Embedded Core Based Processor.

Carolina Miro, Nicolas Darbel, Renaud Pacalet, Valerie Paquet

Proceedings of the 1997 International Conference on Application-Specific Systems, 1997