Renato Stefanelli

According to our database, Renato Stefanelli authored at least 38 papers between 1971 and 2011.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2011

A New Compact SD2 Positive Integer Triangular Array Division Circuit.

Marco D. Santambrogio, Renato Stefanelli

IEEE Trans. Very Large Scale Integr. Syst., 2011

2002

Fault-Tolerant CAM Architectures: A Design Framework.

Fabio Salice, Mariagiovanna Sami, Renato Stefanelli

Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002

1998

Systematic AUED Codes for Self-Checking Architectures.

Donatella Sciuto, Cristina Silvano, Renato Stefanelli

Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998

1997

Array partitioning to achieve defect tolerance.

Fausto Distante, Mariagiovanna Sami, Renato Stefanelli

Proceedings of the 23rd EUROMICRO Conference '97, 1997

Harvesting Through Array Partitioning: A Solution to Achieve Defect Tolerance.

Fausto Distante, Mariagiovanna Sami, Renato Stefanelli

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

Designing Ad-Hoc Codes for the Realization of Fault Tolerant CMOS Networks.

Cristiana Bolchini, Giacomo Buonanno, M. Cozzini, Donatella Sciuto, Renato Stefanelli

Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997

1996

KITE: a behavioural approach to fault-tolerance in FPGA-based systems.

Giovanni A. Mojoli, Davide Salvi, M. G. Sami, Giacomo R. Sechi, Renato Stefanelli

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

Fault detection and fault tolerance issues at CMOS level through AUED encoding.

Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996

1995

A new switching-level approach to multiple-output functions synthesis.

Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A Channel-Constrained Reconfiguration Approach for Processing Arrays.

Mariagiovanna Sami, Fausto Distante, Renato Stefanelli

Proceedings of the 1995 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1995

1994

Innovative Structures for CMOS Combinational Gates Synthesis.

Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

IEEE Trans. Computers, 1994

CMOS Reliability Improvements Through a New Fault Tolerant Technique.

Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

A CMOS Fault Tolerant Architecture for Swith-Level Faults.

Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993

Concurrently self-checking structures for Fsms.

M. G. Sami, Donatella Sciuto, Renato Stefanelli

Microprocess. Microprogramming, 1993

New CMOS Structures for the Synthesis of Dominant Functions.

Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the Sixth International Conference on VLSI Design, 1993

System Level Policies for Fault Tolerance Issues in the FERMI Project.

A. Dell'Acqua, M. Hansen, Sami J. Inkinen, B. Lofstedt, J. P. Vanuxem, Christer Svensson, Jiren Yuan, H. Hentzell, L. Del Buono, J. David, J. F. Genat, H. Lebbolo, O. LeDortz, P. Nayman, Aurore Savoy-Navarro, R. Zitoun, Cesare Alippi, Luca Breveglieri, Luigi Dadda, Vincenzo Piuri, Fabio Salice, Mariagiovanna Sami, Renato Stefanelli, P. Cattaneo, G. Fumagalli, G. Goggi, Simona Brigati, Umberto Gatti, Franco Maloberti, Guido Torelli, P. Carlson, A. Kerek, Goran Appelquist, S. Berglund, C. Bohm, Magnus Engström, N. Yamdagni, Rolf Sundblad, I. Höglund, S. T. Persson

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

Multi-parallel convolvers.

Luigi Dadda, Vincenzo Piuri, Renato Stefanelli

Proceedings of the 11th Symposium on Computer Arithmetic, 29 June, 1993

1992

A behavioral approach to testability analysis for neural networks.

Vincenzo Piuri, Mariagiovanna Sami, Donatella Sciuto, Renato Stefanelli

Microprocess. Microprogramming, 1992

Fault-tolerant techniques for VLSI tree structures.

Vincenzo Piuri, Renato Stefanelli

Microprocess. Microprogramming, 1992

1991

The PAPIA system.

Virginio Cantoni, V. Gesu, Marco Ferretti, Stefano Levialdi, Roberto M. Negrini, Renato Stefanelli

J. VLSI Signal Process., 1991

Mapping neural nets onto a massively parallel architecture: a defect-tolerance solution.

Fausto Distante, Mariagiovanna Sami, Renato Stefanelli, Giancarlo Storti-Gajan

Proc. IEEE, 1991

Concurrent error detection in parallel multipliers and complex arithmetic structures: Remarks on the use of the 3n code.

Vincenzo Piuri, Renato Stefanelli

Microprocessing and Microprogramming, 1991

Optimization techniques for multiple output function synthesis.

Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli

Proceedings of the conference on European design automation, 1991

1990

Area compaction in silicon structures for neural net implementation.

Fausto Distante, M. G. Sami, Renato Stefanelli, Giancarlo Storti Gajani

Microprocessing and Microprogramming, 1990

1989

Reconfiguration of VLSI arrays by covering.

Fabrizio Lombardi, Mariagiovanna Sami, Renato Stefanelli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1989

Fault-tolerance through reconfiguration of VLSI and WSI awards.

Roberto M. Negrini, Mariagiovanna Sami, Renato Stefanelli

MIT Press series in computer systems, MIT Press, ISBN: 978-0-262-14044-7, 1989

1988

An algorithm for functional reconfiguration of fixed-size arrays.

Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1988

Error detection in serial multipliers and in systolic arrays: An approach based upon A★N codes.

Vincenzo Piuri, Renato Stefanelli, Giovanni Traverso

Microprocess. Microprogramming, 1988

Use of redundant binary representation for fault-tolerant arithmetic array processors.

Vincenzo Piuri, Renato Stefanelli

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1987

A Technique for Reconfiguring Two Dimensional VLSI Arrays.

Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli

Proceedings of the 8th IEEE Real-Time Systems Symposium (RTSS '87), 1987

1986

A comment on an investigation into the skeletonization approach of Hilditch.

Renato Stefanelli

Pattern Recognit., 1986

Reconfigurable architectures for VLSI processing arrays.

Mariagiovanna Sami, Renato Stefanelli

Proc. IEEE, 1986

Fault Tolerance Fechniques for Array Structures Used in Supercomputing.

Roberto M. Negrini, Mariagiovanna Sami, Renato Stefanelli

Computer, 1986

1985

PAPIA: Pyramidal architecture for parallel image analysis.

Virginio Cantoni, Marco Ferretti, Stefano Levialdi, Renato Stefanelli

Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1983

A multiplier with multiple error correction capability.

Marco Annaratone, Renato Stefanelli

Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983

1973

Compression algorithms that preserve basic topological features in binary-coded patterns.

Mariagiovanna Sami, Renato Stefanelli

Pattern Recognit., 1973

1972

A Suggestion for a High-Speed Parallel Binary Divider.

Renato Stefanelli

IEEE Trans. Computers, 1972

1971

Some Parallel Thinning Algorithms for Digital Pictures.

Renato Stefanelli, Azriel Rosenfeld

J. ACM, 1971