Remy Cellier

According to our database1, Remy Cellier authored at least 15 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
Artificial neural network-based solution for PSP MOSFET model card extraction.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Advanced Analog Design Optimization: Comparison Between Reinforcement Learning and Heuristic Algorithms.
Proceedings of the 20th International Conference on Synthesis, 2024

2023
Reinforcement Learning for Analog Sizing Optimization.
Proceedings of the 19th International Conference on Synthesis, 2023

2019
Body-biasing considerations with SPAD FDSOI: advantages and drawbacks.
Proceedings of the 49th European Solid-State Device Research Conference, 2019

2018
An integrated 10MHz 3 States Buck converter for fast transient response in 180nm CMOS.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2016
A single switch resonant and quasi-resonant converter suitable for low power applications.
Proceedings of the IECON 2016, 2016

2015
A 40-nm CMOS, 1.1-V, 101-dB Dynamic-Range, 1.7-mW Continuous-Time ΣΔ ADC for a Digital Closed-Loop Class-D Amplifier.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Design guidelines for the integration of Geiger-mode avalanche diodes in standard CMOS technologies.
Microelectron. J., 2015

A 0.35 um CMOS Operational Amplifier Using Multi-Path Frequency Compensation.
J. Low Power Electron., 2015

A time-integration based quenching circuit for Geiger-mode avalanche diodes.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2013
A 40-nm CMOS, 1.1-V, 101-dB DR, 1.7-mW continuous-time ΣΔ ADC for a digital closed-loop class-D amplifier.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
A synchronized self oscillating Class-D amplifier for mobile application.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
Analysis and design of an analog control loop for digital input class D amplifiers.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2009
A 0.01%THD, 70dB PSRR Single Ended Class D using Variable Hysteresis Control for Headphone Amplifiers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A topological comparison of PWM and hysteresis controls in switching audio amplifiers.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008


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