Rei Ueno
Orcid: 0000-0002-9754-6792Affiliations:
- Tohoku University, Sendai, Japan
According to our database1,
Rei Ueno
authored at least 69 papers
between 2014 and 2025.
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Collaborative distances:
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Bibliography
2025
Perceived Information Revisited II Information-Theoretical Analysis of Deep-Learning Based Side-Channel Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025
2024
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024
IACR Cryptol. ePrint Arch., 2024
IACR Commun. Cryptol., 2024
Crystalor: Recoverable Memory Encryption Mechanism with Optimized Metadata Structure.
Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security, 2024
Comparative Analysis and Implementation of Jump Address Masking for Preventing TEE Bypassing Fault Attacks.
Proceedings of the 19th International Conference on Availability, Reliability and Security, 2024
2023
IEEE Trans. Circuits Syst. II Express Briefs, October, 2023
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2023
Crystalor: Persistent Memory Encryption Mechanism with Optimized Metadata Structure and Fast Crash Recovery.
IACR Cryptol. ePrint Arch., 2023
IACR Cryptol. ePrint Arch., 2023
Proceedings of the 53rd IEEE International Symposium on Multiple-Valued Logic, 2023
2022
IEEE Trans. Inf. Forensics Secur., 2022
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
One Truth Prevails: A Deep-learning Based Single-Trace Power Analysis on RSA-CRT with Windowed Exponentiation.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
Bypassing Isolated Execution on RISC-V using Side-Channel-Assisted Fault-Injection and Its Countermeasure.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
Perceived Information Revisited New Metrics to Evaluate Success Rate of Side-Channel Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Efficient Formal Verification of Galois-Field Arithmetic Circuits Using ZDD Representation of Boolean Polynomials.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
On the Success Rate of Side-Channel Attacks on Masked Implementations: Information-Theoretical Bounds and Their Practical Usage.
IACR Cryptol. ePrint Arch., 2022
IACR Cryptol. ePrint Arch., 2022
High-Speed Hardware Architecture for Post-Quantum Diffie-Hellman Key Exchange Based on Residue Number System.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
Proceedings of the 25th Euromicro Conference on Digital System Design, 2022
2021
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE.
IEEE Trans. Inf. Forensics Secur., 2021
Imbalanced Data Problems in Deep Learning-Based Side-Channel Attacks: Analysis and Solution.
IEEE Trans. Inf. Forensics Secur., 2021
J. Cryptogr. Eng., 2021
An Algebraic Approach to Verifying Galois-Field Arithmetic Circuits with Multiple-Valued Characteristics.
IEICE Trans. Inf. Syst., 2021
Fault-Injection Attacks against NIST's Post-Quantum Cryptography Round 3 KEM Candidates.
IACR Cryptol. ePrint Arch., 2021
Toward Optimal Deep-Learning Based Side-Channel Attacks: Probability Concentration Inequality Loss and Its Usage.
IACR Cryptol. ePrint Arch., 2021
A Systematic Design Methodology of Formally Proven Side-Channel-Resistant Cryptographic Hardware.
IEEE Des. Test, 2021
Proceedings of the 51st IEEE International Symposium on Multiple-Valued Logic, 2021
2020
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2020
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Computers, 2020
IACR Cryptol. ePrint Arch., 2020
Debiasing Method for Efficient Ternary Fuzzy Extractors and Ternary Physically Unclonable Functions.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Effective Formal Verification for Galois-field Arithmetic Circuits with Multiple-Valued Characteristics.
Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2020
Practical Side-Channel Based Model Extraction Attack on Tree-Based Machine Learning Algorithm.
Proceedings of the Applied Cryptography and Network Security Workshops, 2020
2019
Efficient Fuzzy Extractors Based on Ternary Debiasing Method for Biased Physically Unclonable Functions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
Tackling Biased PUFs Through Biased Masking: A Debiasing Method for Efficient Fuzzy Extractor.
IEEE Trans. Computers, 2019
Highly efficient GF(2<sup>8</sup>) inversion circuit based on hybrid GF representations.
J. Cryptogr. Eng., 2019
Proceedings of 8th International Workshop on Security Proofs for Embedded Systems, 2019
Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
On Masked Galois-Field Multiplication for Authenticated Encryption Resistant to Side Channel Analysis.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2018
Proceedings of the PROOFS 2018, 2018
2017
IEEE Trans. Computers, 2017
Hierarchical Formal Verification Combining Algebraic Transformation with PPRM Expansion and Its Application to Masked Cryptographic Processors.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017
IEICE Trans. Inf. Syst., 2017
A Systematic Design of Tamper-Resistant Galois-Field Arithmetic Circuits Based on Threshold Implementation with (d + 1) Input Shares.
Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017
Proceedings of the 2017 IEEE European Symposium on Security and Privacy Workshops, 2017
Automatic generation of formally-proven tamper-resistant Galois-field multipliers based on generalized masking scheme.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Toward More Efficient DPA-Resistant AES Hardware Architecture Based on Threshold Implementation.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017
Multiple-Valued Debiasing for Physically Unclonable Functions and Its Application to Fuzzy Extractors.
Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2017
2016
A Formal Verification Method of Error Correction Code Processors Over Galois-Field Arithmetic.
J. Multiple Valued Log. Soft Comput., 2016
A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths - Toward Efficient CBC-Mode Implementation.
IACR Cryptol. ePrint Arch., 2016
Formal Design of Pipelined GF Arithmetic Circuits and Its Application to Cryptographic Processors.
Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016
2015
Efficient DFA on SPN-Based Block Ciphers and Its Application to the LED Block Cipher.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015
Highly Efficient GF(2<sup>8</sup>) Inversion Circuit Based on Redundant GF Arithmetic and Its Application to AES Design.
IACR Cryptol. ePrint Arch., 2015
Formal Design of Galois-Field Arithmetic Circuits Based on Polynomial Ring Representation.
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015
2014
An Efficient Approach to Verifying Galois-Field Arithmetic Circuits of Higher Degrees and Its Application to ECC Decoders.
Proceedings of the IEEE 44th International Symposium on Multiple-Valued Logic, 2014