Razvan Nane

According to our database, Razvan Nane authored at least 24 papers between 2011 and 2023.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2023

An Evaluation and Comparison of GPU Hardware and Solver Libraries for Accelerating the OPM Flow Reservoir Simulator.

Tong Dong Qiu, Andreas Thune, Markus Blatt, Alf Birger Rustad, Razvan Nane

CoRR, 2023

2022

Hardware Acceleration of High-Performance Computational Flow Dynamics Using High-Bandwidth Memory-Enabled Field-Programmable Gate Arrays.

Tom Hogervorst, Razvan Nane, Giacomo Marchiori, Tong Dong Qiu, Markus Blatt, Alf Birger Rustad

ACM Trans. Reconfigurable Technol. Syst., 2022

OpenQL: A Portable Quantum Programming Framework for Quantum Accelerators.

Nader Khammassi, Imran Ashraf, J. van Someren, Razvan Nane, Anna M. Krol, M. A. Rol, Lingling Lao, Koen Bertels, Carmen G. Almudéver

ACM J. Emerg. Technol. Comput. Syst., 2022

SDC-based Resource Constrained Scheduling for Quantum Control Architectures.

Razvan Nane

CoRR, 2022

2021

Hardware Acceleration of HPC Computational Flow Dynamics using HBM-enabled FPGAs.

Tom Hogervorst, Tong Dong Qiu, Giacomo Marchiori, Alf Birger Rustad, Markus Blatt, Razvan Nane

CoRR, 2021

2020

Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures.

Jintao Yu, Razvan Nane, Imran Ashraf, Mottaqiallah Taouil, Said Hamdioui, Henk Corporaal, Koen Bertels

IEEE Trans. Emerg. Top. Comput., 2020

2019

Sparstition: A Partitioning Scheme for Large-Scale Sparse Matrix Vector Multiplication on FPGA.

Björn Sigurbergsson, Tom Hogervorst, Tong Dong Qiu, Razvan Nane

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2017

On the Implementation of Computation-in-Memory Parallel Adder.

Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Razvan Nane, Said Hamdioui, Koen Bertels

IEEE Trans. Very Large Scale Integr. Syst., 2017

A Domain-Specific Language and Compiler for Computation-in-Memory Skeletons.

Jintao Yu, Tom Hogervorst, Razvan Nane

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016

A Survey and Evaluation of FPGA High-Level Synthesis Tools.

Razvan Nane, Vlad Mihai Sima, Christian Pilato, Jongsok Choi, Blair Fort, Andrew Canis, Yu Ting Chen, Hsuan Hsiao, Stephen Dean Brown, Fabrizio Ferrandi, Jason Helge Anderson, Koen Bertels

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

An Image Processing VLIW Architecture for Real-Time Depth Detection.

Dan Iorga, Razvan Nane, Yi Lu, Edwin van Dalen, Koen Bertels

Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Skeleton-based design and simulation flow for Computation-in-Memory architectures.

Jintao Yu, Razvan Nane, Adib Haron, Said Hamdioui, Henk Corporaal, Koen Bertels

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Parallel matrix multiplication on memristor-based computation-in-memory architecture.

Adib Haron, Jintao Yu, Razvan Nane, Mottaqiallah Taouil, Said Hamdioui, Koen Bertels

Proceedings of the International Conference on High Performance Computing & Simulation, 2016

2015

Computation-in-memory based parallel adder.

Hoang Anh Du Nguyen, Lei Xie, Mottaqiallah Taouil, Razvan Nane, Said Hamdioui, Koen Bertels

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Low-Cost Software Control-Flow Error Recovery.

Ghazaleh Nazarian, Razvan Nane, Georgi Gaydadjiev

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014

Automatic Hardware Generation for Reconfigurable Architectures.

Razvan Nane

PhD thesis, 2014

High-Level Synthesis in the Delft Workbench Hardware/Software Co-design Tool-Chain.

Razvan Nane, Vlad Mihai Sima, Cuong Pham-Quoc, Fernando M. Gonçalves, Koen Bertels

Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

2013

Quipu: A Statistical Model for Predicting Hardware Resources.

Roel Meeuws, Sayyed Arash Ostadzadeh, Carlo Galuzzi, Vlad Mihai Sima, Razvan Nane, Koen Bertels

ACM Trans. Reconfigurable Technol. Syst., 2013

Controlling a complete hardware synthesis toolchain with LARA aspects.

João M. P. Cardoso, Tiago Carvalho, José Gabriel F. Coutinho, Ricardo Nobre, Razvan Nane, Pedro C. Diniz, Zlatko Petrov, Wayne Luk, Koen Bertels

Microprocess. Microsystems, 2013

Deriving Resource Efficient Designs Using the REFLECT Aspect-Oriented Approach - (Extended Abstract).

José Gabriel F. Coutinho, João M. P. Cardoso, Tiago Carvalho, Ricardo Nobre, Sujit Bhattacharya, Pedro C. Diniz, Liam Fitzpatrick, Razvan Nane

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2012

A lightweight speculative and predicative scheme for hardware execution.

Razvan Nane, Vlad Mihai Sima, Koen Bertels

Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Area constraint propagation in high level synthesis.

Razvan Nane, Vlad Mihai Sima, Koen Bertels

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

DWARV 2.0: A CoSy-based C-to-VHDL hardware compiler.

Razvan Nane, Vlad Mihai Sima, Bryan Olivier, Roel Meeuws, Yana Yankova, Koen Bertels

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011

IP-XACT extensions for Reconfigurable Computing.

Razvan Nane, Sven van Haastregt, Todor P. Stefanov, Bart Kienhuis, Vlad Mihai Sima, Koen Bertels

Proceedings of the 22nd IEEE International Conference on Application-specific Systems, 2011