Raymond R. Hoare

According to our database, Raymond R. Hoare authored at least 42 papers between 1996 and 2014.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2014

Accelerating SAR processing on COTS FPGA hardware using C-to-gates design tools.

Raymond R. Hoare, Denis Smetana

Proceedings of the IEEE High Performance Extreme Computing Conference, 2014

2008

Radio frequency identification prototyping.

Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle

ACM Trans. Design Autom. Electr. Syst., 2008

A two-stage hardware scheduler combining greedy and optimal scheduling.

Raymond R. Hoare, Zhu Ding, Alex K. Jones

J. Parallel Distributed Comput., 2008

A CAM-based intrusion detection system for single-packet attack detection.

Ying Yu, Raymond R. Hoare, Alex K. Jones

Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007

An automated, FPGA-based reconfigurable, low-power RFID tag.

Alex K. Jones, Raymond Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle

Microprocess. Microsystems, 2007

Linking Compilation and Visualization for Massively Parallel Programs.

Alex K. Jones, Raymond R. Hoare, Joseph St. Onge, Joshua M. Lucas, Shuyi Shao, Rami G. Melhem

Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006

Reducing power while increasing performance with supercisc.

Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster

ACM Trans. Embed. Comput. Syst., 2006

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power.

Alex K. Jones, Raymond R. Hoare, Dara Kusic, Justin Stander, Gayatri Mehta, Joshua Fazekas

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Technology mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).

Joshua M. Lucas, Raymond Hoare, Ivan S. Kourtev, Alex K. Jones

Microprocess. Microsystems, 2006

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.

Gayatri Mehta, Justin Stander, Joshua M. Lucas, Raymond R. Hoare, Brady Hunsaker, Alex K. Jones

J. Low Power Electron., 2006

Passive active radio frequency identification tags.

Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Peter J. Hawrylak, Leonid Mats, Raymond R. Hoare, James T. Cain, Marlin H. Mickle

Int. J. Radio Freq. Identif. Technol. Appl., 2006

Speech Silicon: An FPGA Architecture for Real-Time Hidden Markov-Model-Based Speech Recognition.

Jeffrey William Schuster, Kshitij Gupta, Raymond Hoare, Alex K. Jones

EURASIP J. Embed. Syst., 2006

Rapid VLIW Processor Customization for Signal Processing Applications Using Combinational Hardware Functions.

Raymond R. Hoare, Alex K. Jones, Dara Kusic, Joshua Fazekas, John Foster, Shen Chih Tung, Michael L. McCloud

EURASIP J. Adv. Signal Process., 2006

Interconnect routing and scheduling - A near-optimal real-time hardware scheduler for large cardinality crossbar switches.

Raymond R. Hoare, Zhu Ding, Alex K. Jones

Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

Interconnect routing and scheduling - Level-wise scheduling algorithm for fat tree interconnection networks.

Zhu Ding, Raymond R. Hoare, Alex K. Jones, Rami G. Melhem

Proceedings of the ACM/IEEE SC2006 Conference on High Performance Networking and Computing, 2006

A hybrid encoding scheme for efficient single-cycle range matching in content addressable memory.

Ying Yu, Raymond R. Hoare, Alex K. Jones, Ralph Sprang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Speech silicon AM: an FPGA-based acoustic modeling pipeline for hidden Markov model based speech recognition.

Jeffrey William Schuster, Kshitij Gupta, Raymond R. Hoare

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Design space exploration for low-power reconfigurable fabrics.

Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.

Gayatri Mehta, Raymond R. Hoare, Justin Stander, Alex K. Jones

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

A Field Programmable RFID Tag and Associated Design Flow.

Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Technology Mapping for Field Programmable Gate Arrays using Content-Addressable Memory (CAM).

Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

An automated, reconfigurable, low-power RFID tag.

Alex K. Jones, Raymond R. Hoare, Swapna R. Dontharaju, Shen Chih Tung, Ralph Sprang, Joshua Fazekas, James T. Cain, Marlin H. Mickle

Proceedings of the 43rd Design Automation Conference, 2006

2005

A framework for the design, synthesis and cycle-accurate simulation of multiprocessor networks.

Raymond R. Hoare, Zhu Ding, Shen Chih Tung, Rami G. Melhem, Alex K. Jones

J. Parallel Distributed Comput., 2005

On the Feasibility of Optical Circuit Switching for High Performance Computing Systems.

Kevin J. Barker, Alan F. Benner, Raymond R. Hoare, Adolfy Hoisie, Alex K. Jones, Darren J. Kerbyson, Dan Li, Rami G. Melhem, Ramakrishnan Rajamony, Eugen Schenfeld, Shuyi Shao, Craig B. Stunkel, Peter Walker

Proceedings of the ACM/IEEE SC2005 Conference on High Performance Networking and Computing, 2005

Extracting Speedup From C-Code With Poor Instruction-Level Parallelism.

Dara Kusic, Raymond Hoare, Alex K. Jones, Joshua Fazekas, John Foster

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Switch Design to Enable Predictive Multiplexed Switching in Multiprocessor Networks.

Zhu Ding, Raymond R. Hoare, Alex K. Jones, Dan Li, Shou-Kuo Shao, Shen-Chien Tung, Jiang Zheng, Rami G. Melhem

Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

An FPGA-based VLIW processor with custom hardware execution.

Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Optimizing Technology Mapping for FPGAs Using CAMs.

Joshua M. Lucas, Raymond Hoare, Alex K. Jones

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004

An 88-Way Multiprocessor within an FPGA with Customizable Instructions.

Raymond Hoare, Shen Chih Tung, Katrina Werger

Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

LURU: global-scope FPGA technology mapping with content-addressable memories.

Joshua M. Lucas, Raymond R. Hoare, Ivan S. Kourtev, Alex K. Jones

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

A 64-way VLIW/SIMD FPGA architecture and design flow.

Alex K. Jones, Raymond Hoare, Ivan S. Kourtev, Joshua Fazekas, Dara Kusic, John Foster, Sedric Boddie, Ahmed Muaydh

Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004

2003

Short Courses in System-on-a-Chip (SoC) Design.

Ivan S. Kourtev, Raymond R. Hoare, Steven P. Levitan, Tom Cain, Bruce R. Childers, Donald M. Chiarulli, David L. Landis

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Combining Mentor Graphics? HDL Designer FPGA Flow with a Reconfigurable System on a Programmable Chip, Educational Opportunity or Insanity?

Raymond Hoare, Shen Chih Tung

Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

2002

Cross-institutional assessment: Development and implementation of the On-line Student Survey System.

Raymond Hoare, Mary Besterfield-Sacre, Dan Ertman, Jessica Gerchak, Troy A. Johnson, Robert Shields, Larry J. Shuman

Comput. Appl. Eng. Educ., 2002

A Width Expansion of MMX/SIMD Processing Architecture on an FPGA.

Raymond R. Hoare, D. Swope, S. Bailey

Proceedings of the International Conference on Parallel and Distributed Computing Systems, 2002

An SoC Solution for Massive Parallel Processing.

David Reed, Raymond Hoare

Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

2001

Cyclical Cascade Chains: A Dynamic Barrier Synchronization Mechanism for Multiprocessor Systems.

Troy A. Johnson, Raymond R. Hoare

Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

2000

ClusterNet: An Object-Oriented Cluster Network.

Raymond Hoare

Proceedings of the Parallel and Distributed Processing, 2000

1998

A Case for Aggregate Networks.

Raymond Hoare, Henry G. Dietz

Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998

1997

VLIW Across Multiple Superscalar Processors on a Single Chip.

Soohong P. Kim, Raymond Hoare, Henry G. Dietz

Proceedings of the 1997 Conference on Parallel Architectures and Compilation Techniques (PACT '97), 1997

1996

Bitwise aggregate networks.

Raymond Hoare, Henry G. Dietz, Timothy Mattox, Soohong P. Kim

Proceedings of the Eighth IEEE Symposium on Parallel and Distributed Processing, 1996

A Fine-Grain Parallel Architecture Based on Barrier Synchronization.

Henry G. Dietz, Raymond Hoare, Timothy Mattox

Proceedings of the 1996 International Conference on Parallel Processing, 1996