Raymond E. Siferd

Orcid: 0000-0001-6494-3575

According to our database1, Raymond E. Siferd authored at least 10 papers between 1995 and 2021.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2021
A 170 MHz to 330 MHz Wideband 90 nm CMOS RC-CR Phase Shifter with Integrated On-Line Amplitude Locked Loop Calibration for Hartley Image Rejection Transceiver.
Circuits Syst. Signal Process., 2021

2019
Logistic Function Based Memristor Model With Circuit Application.
IEEE Access, 2019

2011
CMOS 1.6 GHz Bandwidth 12 Bit Time Interleaved Pipelined ADC.
Proceedings of the Eighth International Conference on Information Technology: New Generations, 2011

2009
Performance comparison of two low power wide tuning range VCOs in 90 nm CMOS.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

2004
Parallel time interleaved delta sigma band pass analog to digital converter for SOC applications.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

2003
CMOS VLSI Implementation of a Low-Power Logarithmic Converter.
IEEE Trans. Computers, 2003

VLSI Implementation of a Low-Power Antilogarithmic Converter.
IEEE Trans. Computers, 2003

1999
High Performance CMOS Analog Arithmetic Circuits.
J. VLSI Signal Process., 1999

1996
An Adaptive noise canceler Implemented with CMOS Analog Technology.
J. Circuits Syst. Comput., 1996

1995
Cmos PWM Control Circuit with Programmable Dead Time.
J. Circuits Syst. Comput., 1995


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