Ray C. C. Cheung

John Wong

Clarice Liu

Patrick Hung

Muhammad A. A. Abdelgawad

Proceedings of the Blended Learning. Intelligent Computing in Education, 2024

Design of Light-Weight Encryption Algorithm Based on RISC-V Platform: (PhD Forum Paper).

[BibT_eX]

[DOI]

Zekai Zhang

Ray Chak-Chung Cheung

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

RO-SVD: A Reconfigurable Hardware Copyright Protection Framework for AIGC Applications.

[BibT_eX]

[DOI]

Zhuoheng Ran

Zekai Zhang

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

MSCA: A Multi-Grained Sparse Convolution Accelerator for DNN Training.

[BibT_eX]

[DOI]

Yingchang Mao

Qiang Liu

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023

Efficient Multiple Channels EEG Signal Classification Based on Hierarchical Extreme Learning Machine.

[BibT_eX]

[DOI]

Songyang Lyu

Sensors, November, 2023

High-performance and Configurable SW/HW Co-design of Post-quantum Signature CRYSTALS-Dilithium.

[BibT_eX]

[DOI]

Çetin Kaya Koç

ACM Trans. Reconfigurable Technol. Syst., September, 2023

Efficient and Automatic Breast Cancer Early Diagnosis System Based on the Hierarchical Extreme Learning Machine.

[BibT_eX]

[DOI]

Songyang Lyu

Sensors, September, 2023

Design of a Hippocampal Cognitive Prosthesis Chip.

[BibT_eX]

[DOI]

IEICE Trans. Electron., July, 2023

MUREN: MUltistage Recursive Enhanced Network for Coal-Fired Power Plant Detection.

[BibT_eX]

[DOI]

Remote. Sens., April, 2023

Algorithm-Hardware Co-Design of Split-Radix Discrete Galois Transformation for KyberKEM.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2023

CO-Detector: Towards Complex Object Detection with Cross-Part Feature Learning in Remote Sensing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2023

Image Super-Resolution and FPGA Hardware Design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Signal Processing, 2023

Homomorphic Encryption-Based System Design for Secure Data Processing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Signal Processing, 2023

A Platform for Adaptive Interference Mitigation and Intent Analysis Using OpenLANE.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Signal Processing, 2023

Bidirectionally Deformable Motion Modulation For Video-based Human Pose Transfer.

[BibT_eX]

[DOI]

Proceedings of the IEEE/CVF International Conference on Computer Vision, 2023

In-Network Aggregation with Transport Transparency for Distributed Training.

[BibT_eX]

[DOI]

Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2022

Improved Plantard Arithmetic for Lattice-based Cryptography.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

PipeNTT: A Pipelined Number Theoretic Transform Architecture.

[BibT_eX]

[DOI]

Zewen Ye

Kejie Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2022

High Throughput Hardware/Software Heterogeneous System for RRPN-Based Scene Text Detection.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Machine Learning Based Hardware Architecture for DOA Measurement From Mice EEG.

[BibT_eX]

[DOI]

Mehdi Hasan Chowdhury

Abdelrahman B. M. Eldaly

Stephen Kugbere Agadagba

Leanne Lai-Hang Chan

IEEE Trans. Biomed. Eng., 2022

Reconfigurable content-addressable memory (CAM) on FPGAs: A tutorial and survey.

[BibT_eX]

[DOI]

Muhammad A. A. Abdelgawad

Future Gener. Comput. Syst., 2022

Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2022

A Versatility-Performance Balanced Hardware Architecture for Scene Text Detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE Smartworld, 2022

Melting Glacier: A 37-Year (1984-2020) High-Resolution Glacier-Cover Record of MT. Kilimanjaro.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Geoscience and Remote Sensing Symposium, 2022

Message from the General Chair and Program Co-Chairs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

Preface.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2022

A High-Performance FPGA Accelerator for CUR Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

2021

An Efficient Parallel Processor for Dense Tensor Computation.

[BibT_eX]

[DOI]

Wei-pei Huang

IEEE Trans. Very Large Scale Integr. Syst., 2021

Elastic Net Constraint-Based Tensor Model for High-Order Graph Matching.

[BibT_eX]

[DOI]

IEEE Trans. Cybern., 2021

Scalable Fully Pipelined Hardware Architecture for In-Network Aggregated AllReduce Communication.

[BibT_eX]

[DOI]

Ray Chak-Chung Cheung

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

A systematic review of blockchain scalability: Issues, solutions, analysis and future research.

[BibT_eX]

[DOI]

J. Netw. Comput. Appl., 2021

Accelerated Updating Mechanisms for FPGA-Based Ternary Content-Addressable Memory.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2021

A survey of breakthrough in blockchain technology: Adoptions, applications, challenges and future research.

[BibT_eX]

[DOI]

Ian Huang

Comput. Commun., 2021

Efficient High-Performance FPGA-Redis Hybrid NoSQL Caching System for Blockchain Scalability.

[BibT_eX]

[DOI]

Mehdi Hasan Chowdhury

Comput. Commun., 2021

LoRaWAN-based Camera with (CIRA) Compression and Image Recovery Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE World Forum on Internet of Things, 2021

Aero-Hydroponic Agriculture IoT System.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE World Forum on Internet of Things, 2021

Design of a Battery Carrying Barge for Enhancing Autonomous Sailboat's Endurance Capacity.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Real-time Computing and Robotics, 2021

An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

On the Suitability of Read only Memory for FPGA-Based CAM Emulation Using Partial Reconfiguration.

[BibT_eX]

[DOI]

Kizheppatt Vipin

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020

RPE-TCAM: Reconfigurable Power-Efficient Ternary Content-Addressable Memory on FPGAs.

[BibT_eX]

[DOI]

Mehdi Hasan Chowdhury

IEEE Trans. Very Large Scale Integr. Syst., 2020

Compact Code-Based Signature for Reconfigurable Devices With Side Channel Resilience.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Binary convolutional neural network acceleration framework for rapid system prototyping.

[BibT_eX]

[DOI]

J. Syst. Archit., 2020

NetReduce: RDMA-Compatible In-Network Reduction for Distributed DNN Training Acceleration.

[BibT_eX]

[DOI]

CoRR, 2020

A Highly Parallel Constant-Time Almost-Inverse Algorithm.

[BibT_eX]

[DOI]

Daniele Venier

Proceedings of the IEEE International Conference on Signal Processing, 2020

Dynamic Sparse Training: Find Efficient Sparse Network From Scratch With Trainable Masked Layers.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Learning Representations, 2020

2019

Feature Selection Based on Tensor Decomposition and Object Proposal for Night-Time Multiclass Vehicle Detection.

[BibT_eX]

[DOI]

IEEE Trans. Syst. Man Cybern. Syst., 2019

A robust background initialization algorithm with superpixel motion detection.

[BibT_eX]

[DOI]

Signal Process. Image Commun., 2019

A high performance hardware architecture for non-negative tensor factorization.

[BibT_eX]

[DOI]

Microelectron. J., 2019

High performance hardware architecture for singular spectrum analysis of Hankel tensors.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2019

D-TCAM: A High-Performance Distributed RAM Based TCAM Architecture on FPGAs.

[BibT_eX]

[DOI]

IEEE Access, 2019

High Performance Power-Efficient Gate-Based CAM for Reconfigurable Computing.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Mobile Ad-Hoc and Sensor Networks, 2019

Reconfigurable RISC-V Secure Processor And SoC Integration.

[BibT_eX]

[DOI]

Zhenya Zang

Yao Liu

Proceedings of the IEEE International Conference on Industrial Technology, 2019

Optimized Polynomial Multiplier Over Commutative Rings on FPGAs: A Case Study on BIKE.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2019

Accurate and Compact Convolutional Neural Networks with Trained Binarization.

[BibT_eX]

[DOI]

Proceedings of the 30th British Machine Vision Conference 2019, 2019

An Efficient Application Specific Instruction Set Processor (ASIP) for Tensor Computation.

[BibT_eX]

[DOI]

Wei-pei Huang

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

Bank-selective Strategy for Gate-based Ternary Content-addressable Memory on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International Conference on Application-specific Systems, 2019

2018

High-Speed Discrete Gaussian Sampler With Heterodyne Chaotic Laser Inputs.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2018

FFT-Based McLaughlin's Montgomery Exponentiation without Conditional Selections.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

A fast inter CU decision algorithm for HEVC.

[BibT_eX]

[DOI]

Signal Process. Image Commun., 2018

ASIC Implementation of a Nonlinear Dynamical Model for Hippocampal Prosthesis.

[BibT_eX]

[DOI]

Neural Comput., 2018

Spectral arithmetic in Montgomery modular multiplication.

[BibT_eX]

[DOI]

Wangchen Dai

J. Cryptogr. Eng., 2018

Dynamic Virtual Page-Based Flash Translation Layer With Novel Hot Data Identification and Adaptive Parallelism Management.

[BibT_eX]

[DOI]

Qiwu Luo

Yichuang Sun

IEEE Access, 2018

Lightweight Secure Processor Prototype on FPGA.

[BibT_eX]

[DOI]

Yao Liu

Hei Wong

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

2017

A Fully Pipelined Hardware Architecture for Intra Prediction of HEVC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2017

A Bias-Bounded Digital True Random Number Generator Architecture.

[BibT_eX]

[DOI]

Yao Liu

Hei Wong

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Compact Constant Weight Coding Engines for the Code-Based Cryptography.

[BibT_eX]

[DOI]

Jingwei Hu

Tim Güneysu

IEEE Trans. Circuits Syst. II Express Briefs, 2017

Toward Practical Code-Based Signature: Implementing Fast and Compact QC-LDGM Signature Scheme on Embedded Hardware.

[BibT_eX]

[DOI]

Jingwei Hu

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Area-Time Efficient Computation of Niederreiter Encryption on QC-MDPC Codes for Embedded Hardware.

[BibT_eX]

[DOI]

Jingwei Hu

IEEE Trans. Computers, 2017

Area-Time Efficient Architecture of FFT-Based Montgomery Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2017

A low power V-band LC VCO with high Q varactor technique in 40 nm CMOS process.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2017

Fast HEVC intra coding decision based on statistical cost and corner detection.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Systems, Signals and Image Processing, 2017

High DC gain and wide output swing class-C inverter.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2017

2016

Parameter Space for the Architecture of FFT-Based Montgomery Modular Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2016

An FPGA-Based High-Performance Neural Ensemble Spiking Activity Simulator Utilizing Generalized Volterra Kernel and Complexity Analysis.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2016

FPGA-Based High-Performance Collision Detection: An Enabling Technique for Image-Guided Robotic Surgery.

[BibT_eX]

[DOI]

Frontiers Robotics AI, 2016

2015

Z-TCAM: An SRAM-based Architecture for TCAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Fast CU Size Decision Algorithm for the HEVC Intra Encoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2015

An Application Specific Instruction Set Processor (ASIP) for Adaptive Filters in Neural Prosthetics.

[BibT_eX]

[DOI]

IEEE ACM Trans. Comput. Biol. Bioinform., 2015

Configurable Architectures for Multi-Mode Floating Point Adders.

[BibT_eX]

[DOI]

B. Sharat Chandra Varma

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Fast and Generic Inversion Architectures Over GF(2m) Using Modified Itoh-Tsujii Algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2015

High-Speed Polynomial Multiplication Architecture for Ring-LWE and SHE Cryptosystems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Architecture Support for Task Out-of-Order Execution in MPSoCs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Efficient Pairing Computation on Huff Curves.

[BibT_eX]

[DOI]

Cryptologia, 2015

2014

Design Exploration of Geometric Biclustering for Microarray Data Analysis in Data Mining.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2014

Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Novel RNS Parameter Selection for Fast Modular Multiplication.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2014

An FPGA based scalable architecture of a stochastic state point process filter (SSPPF) to track the nonlinear dynamics underlying neural spiking.

[BibT_eX]

[DOI]

Microelectron. J., 2014

GPU-based biclustering for microarray data analysis in neurocomputing.

[BibT_eX]

[DOI]

Neurocomputing, 2014

A perfectly current matched charge pump with wide dynamic range for ultra low voltage applications.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

E-TCAM: An Efficient SRAM-Based Architecture for TCAM.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2014

Series Expansion based Efficient Architectures for Double Precision Floating Point Division.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2014

A low-power inverter-based ΣΔ analog-to-digital converter for audio applications.

[BibT_eX]

[DOI]

Sci. China Inf. Sci., 2014

Configurable Architecture for Double/Two-Parallel Single Precision Floating Point Division.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Zero collision attack and its countermeasures on Residue Number System multipliers.

[BibT_eX]

[DOI]

Marc Stöttinger

Gavin Xiaoxu Yao

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

VLSI architecture of a high-performance neural spiking activity simulator based on generalized Volterra kernel.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Time-efficient computation of digit serial Montgomery multiplication.

[BibT_eX]

[DOI]

Wangchen Dai

Huapeng Wu

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

Trade-offs between the sensitivity and the speed of the FPGA-based sequence aligner.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A complementary architecture for high-speed true random number generator.

[BibT_eX]

[DOI]

Xian Yang

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Big data genome sequencing on Zynq based clusters (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Laguerre-volterra model and architecture for MIMO system identification and output prediction.

[BibT_eX]

[DOI]

Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

2013

A Flexible and Customizable Architecture for the Relaxation Labeling Algorithm.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Real-Time Prediction of Neuronal Population Spiking Activity Using FPGA.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2013

HEALPIX DCT technique for compressing PCA-based illumination adjustable images.

[BibT_eX]

[DOI]

Neural Comput. Appl., 2013

Parallel architecture for DNA sequence inexact matching with Burrows-Wheeler Transform.

[BibT_eX]

[DOI]

Microelectron. J., 2013

Area-efficient architectures for double precision multiplier on FPGA, with run-time-reconfigurable dual single precision support.

[BibT_eX]

[DOI]

Microelectron. J., 2013

A 0.8-V 230-µW 98-dB DR Inverter-Based ΣΔ Modulator for Audio Applications.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A σδ modulator using gain-Boost Class-C Inverter for Audio Applications.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2013

A scalable RNS Montgomery multiplier over F2m.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2013

VLSI Implementation of Double-Precision Floating-Point Multiplier Using Karatsuba Technique.

[BibT_eX]

[DOI]

Circuits Syst. Signal Process., 2013

A memory-based NFA regular expression match engine for signature-based intrusion detection.

[BibT_eX]

[DOI]

Derek Chi-Wai Pao

Nga Lam Or

Comput. Commun., 2013

Design Automation Framework for Reconfigurable Interconnection Networks.

[BibT_eX]

[DOI]

Hongbing Fan

Comput. J., 2013

A reconfigurable architecture for real-time prediction of neural activity.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Noise filtering and occurrence identification of mouse ultrasonic vocalization call.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Machine Learning and Cybernetics, 2013

Fast simulation of Digital Spiking Silicon Neuron model employing reconfigurable dataflow computing.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Design space explorations of Hybrid-Partitioned TCAM (HP-TCAM).

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Genome sequencing using mapreduce on FPGA with multiple hardware accelerators (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

A customizable Stochastic State Point Process Filter (SSPPF) for neural spiking activity.

[BibT_eX]

[DOI]

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012

Hypergraph based geometric biclustering algorithm.

[BibT_eX]

[DOI]

Pattern Recognit. Lett., 2012

Subthreshold CMOS voltage reference circuit with body bias compensation for process variation.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2012

Faster Pairing Coprocessor Architecture.

[BibT_eX]

[DOI]

Proceedings of the Pairing-Based Cryptography - Pairing 2012, 2012

An FPGA-based acceleration platform for auction algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

FPGA Implementation of SRAM-based Ternary Content Addressable Memory.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

Area-Efficient FPGA Implementation of Quadruple Precision Floating Point Multiplier.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

GPU-Based Biclustering for Neural Information Processing.

[BibT_eX]

[DOI]

Alan W. Y. Lo

Benben Liu

Proceedings of the Neural Information Processing - 19th International Conference, 2012

Low complexity and hardware-friendly spectral modular multiplication.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Area-Efficient Architectures for Large Integer and Quadruple Precision Floating Point Multipliers.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

A dual mode FPGA design for the hippocampal prosthesis.

[BibT_eX]

[DOI]

Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

High Performance Reconfigurable Architecture for Double Precision Floating Point Division.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

A High Speed Pairing Coprocessor Using RNS and Lazy Reduction.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2011

High-Performance and Scalable System Architecture for the Real-Time Estimation of Generalized Laguerre-Volterra MIMO Model From Neural Population Spiking Activity.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Rapid single-chip secure processor prototyping on the OpenSPARC FPGA platform.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Hydrate: Hybrid Reconfigurable Architecture Expressions.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Activities.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

FPGA Architecture of Generalized Laguerre-Volterra MIMO Model for Neural Population Spiking Activities.

[BibT_eX]

[DOI]

Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

A hardware-based computational platform for Generalized Laguerre-Volterra MIMO model for neural activities.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction.

[BibT_eX]

[DOI]

Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010

Counter Embedded Memory architecture for trusted computing platform.

[BibT_eX]

[DOI]

Gavin Xiaoxu Yao

Kim-Fung Man

Proceedings of the 21st IEEE International Symposium on Rapid System Prototyping, 2010

Reconfigurable Number Theoretic Transform architectures for cryptographic applications.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

Design Automation for Reconfigurable Interconnection Networks.

[BibT_eX]

[DOI]

Hongbing Fan

Chak-Chung Cheung

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Hierarchical Segmentation for Hardware Function Evaluation.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2009

A High-Performance Hardware Architecture for Spectral Hash Algorithm.

[BibT_eX]

[DOI]

Çetin Kaya Koç

John D. Villasenor

Proceedings of the 20th IEEE International Conference on Application-Specific Systems, 2009

2008

Hardware Implementation Trade-Offs of Polynomial Approximations and Interpolations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

2007

A Flexible Architecture for Precise Gamma Correction.

[BibT_eX]

[DOI]

Dong-U Lee

John D. Villasenor

IEEE Trans. Very Large Scale Integr. Syst., 2007

Hardware Generation of Arbitrary Random Number Distributions From Uniform Distributions Via the Inversion Method.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

The exact channel density and compound design for generic universal switch blocks.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

Instrumented Multi-Stage Word-Length Optimization.

[BibT_eX]

[DOI]

William George Osborne

José Gabriel F. Coutinho

Oskar Mencer

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

Automatic Accuracy-Guaranteed Bit-Width Optimization for Fixed and Floating-Point Systems.

[BibT_eX]

[DOI]

William George Osborne

José Gabriel F. Coutinho

Oskar Mencer

Proceedings of the FPL 2007, 2007

2006

Accuracy-Guaranteed Bit-Width Optimization.

[BibT_eX]

[DOI]

George A. Constantinides

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Decomposition Design Theory and Methodology for Arbitrary-Shaped Switch Boxes.

[BibT_eX]

[DOI]

Hongbing Fan

Ray Chak-Chung Cheung

Jiping Liu

IEEE Trans. Computers, 2006

Inversion-based hardware gaussian random number generator: A case study of function evaluation via hierarchical segmentation.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

2005

Customizable elliptic curve cryptosystems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

Reconfigurable Acceleration for Monte Carlo Based Financial Simulation.

[BibT_eX]

Guanglie Zhang

Philip Heng Wai Leong

Proceedings of the 2005 IEEE International Conference on Field-Programmable Technology, 2005

Ziggurat-based Hardware Gaussian Random Number Generator.

[BibT_eX]

[DOI]

Guanglie Zhang

Philip Heng Wai Leong

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Reconfigurable Elliptic Curve Cryptosystems on a Chip.

[BibT_eX]

[DOI]

Peter Y. K. Cheung

Proceedings of the 2005 Design, 2005

Automating custom-precision function evaluation for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Compilers, 2005

2004

Customising Hardware Designs for Elliptic Curve Cryptography.

[BibT_eX]

[DOI]

Nicolas Telle

Proceedings of the Computer Systems: Architectures, 2004

A scalable hardware architecture for prime number validation.

[BibT_eX]

[DOI]

Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

On Optimal Irregular Switch Box Designs.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

2003

Further improve circuit partitioning using GBAW logic perturbation techniques.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

On optimal hyperuniversal and rearrangeable switch box designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

An FPGA-based re-configurable 24-bit 96kHz sigma-delta audio DAC.

[BibT_eX]

[DOI]

Philip Heng Wai Leong

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

2002

On Optimum Designs of Universal Switch Blocks.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

Further improve circuit partitioning using GBAW logic perturbation techniques.

[BibT_eX]

[DOI]

Chak-Chung Cheung