Raviteja Theertham

According to our database, Raviteja Theertham authored at least 10 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A -90-dBFS-IM₃, -164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors.

Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Prawal Shrestha, Zhao Li, Sevil Zeynep Lulec, Konstantinos Vasilakopoulos, Raviteja Theertham, Donald Paterson, Qingnan Yu, Aseer Chowdhury

IEEE J. Solid State Circuits, December, 2024

22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors.

Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2023

A 1-MHz-Bandwidth Continuous-Time Delta-Sigma ADC Achieving >90dB SFDR and >80dB Antialiasing Using Reference-Switched Resistive Feedback DACs.

Sharvil Patil, Raviteja Theertham, Hajime Shibata, Victor Kozlov, Asha Ganesan, Efram Burlingame, Zhao Li, Rama Thakar, Qianqian Zhang, Yue Yin, Aathreya S. Bhat

Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022

Alias Rejection in CT Delta-Sigma ADCs Using Virtual-Ground-Switched Resistor Feedback.

Raviteja Theertham, Shanthi Pavan

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Design of High-Resolution Continuous-Time Delta-Sigma Data Converters With Dual Return-to-Open DACs.

Raviteja Theertham, Satya Narayana Ganta, Shanthi Pavan

IEEE J. Solid State Circuits, 2022

A 0.37mm² 250kHz-BW 95dB-SNDR CTDSM with Low-Cost 2^nd-order Vector-Quantizer DEM.

Wei Shi, Xing Wang, Xiyuan Tang, Abhishek Mukherjee, Raviteja Theertham, Shanthi Pavan, Lu Jie, Nan Sun

Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2020

Design Techniques for High-Resolution Continuous-Time Delta-Sigma Converters With Low In-Band Noise Spectral Density.

Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan

IEEE J. Solid State Circuits, 2020

2019

Unified Analysis, Modeling, and Simulation of Chopping Artifacts in Continuous-Time Delta-Sigma Modulators.

Raviteja Theertham, Shanthi Pavan

IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Improved Offline Calibration of DAC Mismatch Errors in Delta-Sigma Data Converters.

Shanthi Pavan, Raviteja Theertham

IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 24mW Chopped CTDSM Achieving 103.5dB SNDR and 107.5dB DR in a 250kHz Bandwidth.

Raviteja Theertham, Prasanth Koottala, Sujith Billa, Shanthi Pavan

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019