Raviteja P. Reddy

According to our database1, Raviteja P. Reddy authored at least 5 papers between 2017 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A Hierarchical Fault-Tolerant and Cost Effective Framework for RRAM Based Neural Computing Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2022

2020
A Cost-Aware Framework for Lifetime Reliability of TSV-Based 3D-IC Design.
IEEE Trans. Circuits Syst., 2020

2019
A Framework for TSV Based 3D-IC to Analyze Aging and TSV Thermo-Mechanical Stress on Soft Errors.
Proceedings of the IEEE International Test Conference in Asia, 2019

Fault Tolerance in 3D-ICs.
Proceedings of the Security and Fault Tolerance in Internet of Things, 2019

2017
A Cost-Effective Fault Tolerance Technique for Functional TSV in 3-D ICs.
IEEE Trans. Very Large Scale Integr. Syst., 2017


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