Raviteja Kammari

According to our database, Raviteja Kammari authored at least 7 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2024

A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End.

Rakesh Varma Rena, Raviteja Kammari, Vijay Shankar Pasupureddi

IEEE Trans. Very Large Scale Integr. Syst., March, 2024

2023

An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects.

Prema Kumar Govindaswamy, Raviteja Kammari, Vijaya Sankara Rao Pasupureddi

Int. J. Circuit Theory Appl., August, 2023

0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS.

Rakesh Varma Rena, Raviteja Kammari, Vijay Shankar Pasupureddi

IEEE Trans. Very Large Scale Integr. Syst., 2023

A 1-6 GHz, Sub-mW Self-Aligned Quadrature Phase Clock Generator in 1.2 V, 65 nm CMOS.

Raviteja Kammari, Sarvesh Rajesh Tuckely, Vijay Shankar Pasupureddi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022

Digitally Intensive Sub-sampling Mixer-First Direct Down-Conversion Receiver Architecture.

Rakesh Rena, Raviteja Kammari, Vijaya Sankara Rao Pasupureddi

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2020

Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS.

Raviteja Kammari, Vijaya Sankara Rao Pasupureddi

Int. J. Circuit Theory Appl., 2020

2019

A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS.

Raviteja Kammari, Vijaya Sankara Rao Pasupureddi

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019