Raviteja Kammari

Orcid: 0000-0002-4792-7167

According to our database1, Raviteja Kammari authored at least 7 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
A 0.4-1.8-GHz Quarter-Rate Subsampling Mixer-First Direct Down-Conversion RF Front-End.
IEEE Trans. Very Large Scale Integr. Syst., March, 2024

2023
An adaptive link training based hybrid circuit topology for full-duplex on-chip interconnects.
Int. J. Circuit Theory Appl., August, 2023

0.4-1 GHz Subsampling Mixer-First RF Front-End With 50-dB HRR, +10-dBm IB-IIP3 in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2023

A 1-6 GHz, Sub-mW Self-Aligned Quadrature Phase Clock Generator in 1.2 V, 65 nm CMOS.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2023

2022
Digitally Intensive Sub-sampling Mixer-First Direct Down-Conversion Receiver Architecture.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2020
Charge controlled delay element enabled widely linear power efficient MPCG-MDLL in 1.2V, 65nm CMOS.
Int. J. Circuit Theory Appl., 2020

2019
A Widely Linear, Power Efficient, Charge Controlled Delay Element for Multi-phase Clock Generation in 1.2 V, 65 nm CMOS.
Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019


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