Ravishankar Arunachalam

According to our database1, Ravishankar Arunachalam authored at least 9 papers between 1997 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2005
Novel Algorithm for Testing Crosstalk Induced Delay Faults in VLSI Circuits.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004
Static Transition Probability Analysis Under Uncertainty.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003
Optimal shielding/spacing metrics for low power design.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Predicting short circuit power from timing models.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation.
VLSI Design, 2002

2001
False Coupling Interactions in Static Timing Analysis.
Proceedings of the 38th Design Automation Conference, 2001

2000
TACO: timing analysis with coupling.
Proceedings of the 37th Conference on Design Automation, 2000

1998
Determination of worst-case aggressor alignment for delay calculation.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

1997
CMOS Gate Delay Models for General RLC Loading.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997


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