Ravi R. Iyer
Orcid: 0000-0001-5383-9561Affiliations:
- Intel Labs, Hillsboro, OR, USA
According to our database1,
Ravi R. Iyer
authored at least 142 papers
between 1997 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2015, "For contributions to computer architecture and cache/memory systems".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
On csauthors.net:
Bibliography
2024
2023
Neurocomputing, November, 2023
IEEE Trans. Computers, June, 2023
Intent-Driven Orchestration: Enforcing Service Level Objectives for Cloud Native Deployments.
SN Comput. Sci., May, 2023
Quantization for Bayesian Deep Learning: Low-Precision Characterization and Robustness.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023
Proceedings of the Asian Conference on Machine Learning, 2023
2022
Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022
DPM-NFV: Dynamic Power Management Framework for 5G User Plane Function using Bayesian Optimization.
Proceedings of the IEEE Global Communications Conference, 2022
2021
IEEE Micro, 2021
CoRR, 2021
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021
Proceedings of the IEEE International Conference on Networking, Architecture and Storage, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
RLDRM: Closed Loop Dynamic Cache Allocation with Deep Reinforcement Learning for Network Function Virtualization.
Proceedings of the 6th IEEE Conference on Network Softwarization, 2020
2019
IEEE Micro, 2019
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019
2018
A Systematic and Realistic Network-on-Chip Traffic Modeling and Generation Technique for Emerging Many-Core Systems.
IEEE Trans. Multi Scale Comput. Syst., 2018
2017
QoS Management on Heterogeneous Architecture for Multiprogrammed, Parallel, and Domain-Specific Applications.
IEEE Syst. J., 2017
IEEE Micro, 2017
Race-to-sleep + content caching + display caching: a recipe for energy-efficient video streaming on handhelds.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017
2016
Visual IoT: Architectural Challenges and Opportunities; Toward a Self-Learning and Energy-Neutral IoT.
IEEE Micro, 2016
Proceedings of the 2016 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Science, 2016
The convergence of physical/digital worlds: implications on workloads & architecture.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016
Cache QoS: From concept to reality in the Intel® Xeon® processor E5-2600 v3 product family.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
2015
Proceedings of the 2015 IEEE Winter Conference on Applications of Computer Vision, 2015
Proceedings of the 23rd Annual ACM Conference on Multimedia Conference, MM '15, Brisbane, Australia, October 26, 2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
Platform-aware dynamic configuration support for efficient text processing on heterogeneous system.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
A Case Study on the Communication and Computation Behaviors of Real Applications in NoC-Based MPSoCs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Reducing cache and TLB power by exploiting memory region and privilege level semantics.
J. Syst. Archit., 2013
Proceedings of the IEEE/ACM 6th International Conference on Utility and Cloud Computing, 2013
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013
Proceedings of the 19th IEEE International Conference on Parallel and Distributed Systems, 2013
OWL: cooperative thread array aware scheduling techniques for improving GPGPU performance.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013
2012
ACM Trans. Archit. Code Optim., 2012
Proceedings of the first edition of the MCC workshop on Mobile cloud computing, 2012
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Exploiting Semantics of Virtual Memory to Improve the Efficiency of the On-Chip Memory System.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
Optimizing datacenter power with memory system levers for guaranteed quality-of-service.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012
2011
ACM SIGOPS Oper. Syst. Rev., 2011
IEEE Micro, 2011
J. Parallel Distributed Comput., 2011
J. Parallel Distributed Comput., 2011
IEEE Des. Test Comput., 2011
Proceedings of the SIGMETRICS 2011, 2011
Proceedings of the IEEE 9th Symposium on Application Specific Processors, 2011
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011
Shared Resource Monitoring and Throughput Optimization in Cloud-Computing Datacenters.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011
Proceedings of the 25th International Conference on Supercomputing, 2011, Tucson, AZ, USA, May 31, 2011
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011
Buffer-integrated-Cache: a cost-effective SRAM architecture for handheld and embedded platforms.
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
2010
ACM Trans. Archit. Code Optim., 2010
SIGMETRICS Perform. Evaluation Rev., 2010
Performance characterization and acceleration of Optical Character Recognition on handheld platforms.
Proceedings of the 2010 IEEE International Symposium on Workload Characterization, 2010
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010
NCID: a non-inclusive cache, inclusive directory architecture for flexible and efficient cache hierarchies.
Proceedings of the 7th Conference on Computing Frontiers, 2010
2009
SIGMETRICS Perform. Evaluation Rev., 2009
SIGMETRICS Perform. Evaluation Rev., 2009
Comput. Networks, 2009
Proceedings of the International Conference on Networking, Architecture, and Storage, 2009
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009
Performance characterization and optimization of mobile augmented reality on handheld platforms.
Proceedings of the 2009 IEEE International Symposium on Workload Characterization, 2009
Proceedings of the 23rd international conference on Supercomputing, 2009
Proceedings of the 27th International Conference on Computer Design, 2009
Using checksum to reduce power consumption of display systems for low-motion content.
Proceedings of the 27th International Conference on Computer Design, 2009
Optimizing communication and capacity in a 3D stacked reconfigurable cache hierarchy.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009
Proceedings of the 16th International Conference on High Performance Computing, 2009
Architecture Support for Improving Bulk Memory Copying and Initialization Performance.
Proceedings of the PACT 2009, 2009
2008
SIGARCH Comput. Archit. News, 2008
SIGARCH Comput. Archit. News, 2008
Proceedings of the 4th International Conference on Virtual Execution Environments, 2008
Proceedings of the 4th International Symposium on Workload Characterization (IISWC 2008), 2008
Performance and power optimization through data compression in Network-on-Chip architectures.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008
Proceedings of the High Performance Computing, 2008
To Snoop or Not to Snoop: Evaluation of Fine-Grain and Coarse-Grain Snoop Filtering Techniques.
Proceedings of the Euro-Par 2008, 2008
2007
IEEE Trans. Parallel Distributed Syst., 2007
IEEE Trans. Computers, 2007
SIGARCH Comput. Archit. News, 2007
Proceedings of the 3rd International Conference on Virtual Execution Environments, 2007
Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-40 2007), 2007
Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007
Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance.
Proceedings of the 2007 IEEE International Symposium on Performance Analysis of Systems and Software, 2007
Proceedings of the IEEE 10th International Symposium on Workload Characterization, 2007
Proceedings of the 25th International Conference on Computer Design, 2007
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007
Proceedings of the High Performance Computing, 2007
Proceedings of the High Performance Computing, 2007
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007
2006
Molecular Caches: A caching structure for dynamic creation of application-specific Heterogeneous cache regions.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006
Proceedings of the Frontiers of High Performance Computing and Networking, 2006
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006
Proceedings of the High Performance Computing, 2006
Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource.
Proceedings of the 15th International Conference on Parallel Architectures and Compilation Techniques (PACT 2006), 2006
2005
SIGARCH Comput. Archit. News, 2005
An Experimental Evaluation of the HP V-Class and SGI Origin 2000 Multiprocessors using Microbenchmarks and Scientific Applications.
Int. J. Parallel Program., 2005
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005
Proceedings of the 32st International Symposium on Computer Architecture (ISCA 2005), 2005
Proceedings of the 24th IEEE International Performance Computing and Communications Conference, 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Proceedings of the 13th Annual IEEE Symposium on High Performance Interconnects (HOTIC 2005), 2005
Proceedings of the Global Telecommunications Conference, 2005. GLOBECOM '05, St. Louis, Missouri, USA, 28 November, 2005
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005
2004
World Wide Web, 2004
Proceedings of the 12th International Workshop on Modeling, 2004
Proceedings of the 18th Annual International Conference on Supercomputing, 2004
Proceedings of the 33rd International Conference on Parallel Processing (ICPP 2004), 2004
Architectural Characterization of TCP/IP Packet Processing on the Pentium M Microprocessor.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004
2003
Proceedings of the 11th International Workshop on Modeling, 2003
2002
Design and analysis of static memory management policies for CC-NUMA multiprocessors.
J. Syst. Archit., 2002
Comparing the Memory System Performance of DSS Workloads on the HP V-Class and SGI Origin 2000.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002
2001
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
2000
Impact of CC-NUMA Memory Management Policies on the Application Performance of Multistage Switching Networks.
IEEE Trans. Parallel Distributed Syst., 2000
IEEE Trans. Computers, 2000
Using Switch Directories to Speed Up Cache-to-Cache Transfers in CC-NUMA Multiprocessors.
Proceedings of the 14th International Parallel & Distributed Processing Symposium (IPDPS'00), 2000
1999
Comparing the memory system performance of the HP V-class and SGI Origin 2000 multiprocessors using microbenchmarks and scientific applications.
Proceedings of the 13th international conference on Supercomputing, 1999
Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999
1998
Impact of Switch Design on the Application Performance of Cache-Coherent Multiprocessors.
Proceedings of the 12th International Parallel Processing Symposium / 9th Symposium on Parallel and Distributed Processing (IPPS/SPDP '98), March 30, 1998
1997
Performance of Multistage Bus Networks for a Distributed Shared Memory Multiprocessor.
IEEE Trans. Parallel Distributed Syst., 1997