Ravi Bhargava

Orcid: 0009-0003-6956-5149

According to our database1, Ravi Bhargava authored at least 15 papers between 1998 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2024
AMD Next-Generation "Zen 4" Core and 4th Gen AMD EPYC Server CPUs.
IEEE Micro, 2024

2023
Machine learning hypothesis-generation for patient stratification and target discovery in rare disease: our experience with Open Science in ALS.
Frontiers Comput. Neurosci., 2023

AMD Next Generation "Zen 4" Core and 4th Gen AMD EPYC™ 9004 Server CPU.
Proceedings of the 35th IEEE Hot Chips Symposium, 2023

2019
Building sankie: an AI platform for DevOps.
Proceedings of the 1st International Workshop on Bots in Software Engineering, 2019

2016
Speculative path power estimation using trace-driven simulations during high-level design phase.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2008
Accelerating two-dimensional page walks for virtualized systems.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2005
Adapting branch-target buffer to improve the target predictability of java code.
ACM Trans. Archit. Code Optim., 2005

2003
The Role of Return Value Prediction in Exploiting Speculative Method-Level Parallelism.
J. Instr. Level Parallelism, 2003

Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

2002
Latency and energy aware value prediction for high-frequency processors.
Proceedings of the 16th international conference on Supercomputing, 2002

Rehashable BTB: An Adaptive Branch Target Buffer to Improve the Target Predictability of Java Code.
Proceedings of the High Performance Computing, 2002

2001
Improving Java performance using hardware translation.
Proceedings of the 15th international conference on Supercomputing, 2001

2000
Issues in the design of store buffers in dynamically scheduled processors.
Proceedings of the 2000 IEEE International Symposium on Performance Analysis of Systems and Software, 2000

1999
Accurately modeling speculative instruction fetching in trace-driven simulation.
Proceedings of the IEEE International Performance Computing and Communications Conference, 1999

1998
Evaluating MMX Technology Using DSP and Multimedia Applications.
Proceedings of the 31st Annual IEEE/ACM International Symposium on Microarchitecture, 1998


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