Rashmi S. Agrawal

Orcid: 0000-0002-9461-0170

Affiliations:
  • Boston University, Department of Electrical and Computer Engineering, MA, USA


According to our database1, Rashmi S. Agrawal authored at least 24 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
HEAP: A Fully Homomorphic Encryption Accelerator with Parallelized Bootstrapping.
Proceedings of the 51st ACM/IEEE Annual International Symposium on Computer Architecture, 2024

2023
RISE: RISC-V SoC for En/Decryption Acceleration on the Edge for Homomorphic Encryption.
IEEE Trans. Very Large Scale Integr. Syst., October, 2023

Hardware accelerators for post-quantum cryptography and fully homomorphic encryption
PhD thesis, 2023

Accelerating Finite Field Arithmetic for Homomorphic Encryption on GPUs.
IEEE Micro, 2023

High-precision RNS-CKKS on fixed but smaller word-size architectures: theory and application.
IACR Cryptol. ePrint Arch., 2023

GME: GPU-based Microarchitectural Extensions to Accelerate Homomorphic Encryption.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

MAD: Memory-Aware Design Techniques for Accelerating Fully Homomorphic Encryption.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

FAB: An FPGA-based Accelerator for Bootstrappable Fully Homomorphic Encryption.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2023

2022
Accelerating Polynomial Multiplication for Homomorphic Encryption on GPUs.
Proceedings of the 2022 IEEE International Symposium on Secure and Private Execution Environment Design (SEED), 2022

RACE: RISC-V SoC for En/decryption Acceleration on the Edge for Homomorphic Computation.
Proceedings of the ISLPED '22: ACM/IEEE International Symposium on Low Power Electronics and Design, Boston, MA, USA, August 1, 2022

Efficient FPGA-based ECDSA Verification Engine for Permissioned Blockchains.
Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021
Does Fully Homomorphic Encryption Need Compute Acceleration?
IACR Cryptol. ePrint Arch., 2021

2020
Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption.
CoRR, 2020

Quantum-Proof Lightweight McEliece Cryptosystem Co-processor Design.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Homomorphic Encryption Based Secure Sensor Data Processing.
Proceedings of the 2020 IEEE High Performance Extreme Computing Conference, 2020

A Post-Quantum Secure Discrete Gaussian Noise Sampler.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

Towards Programmable All-Digital True Random Number Generator.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

Fast Arithmetic Hardware Library For RLWE-Based Homomorphic Encryption.
Proceedings of the 28th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2020

Design-flow Methodology for Secure Group Anonymous Authentication.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Post-Quantum Cryptographic Hardware Primitives.
CoRR, 2019

A Lightweight McEliece Cryptosystem Co-processor Design.
CoRR, 2019

The BRISC-V Platform: A Practical Teaching Approach for Computer Architecture.
Proceedings of the Workshop on Computer Architecture Education, 2019

Open-Source FPGA Implementation of Post-Quantum Cryptographic Hardware Primitives.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2017
Fast Processing of Large Graph Applications Using Asynchronous Architecture.
CoRR, 2017


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