Raphael Martins Brum

Orcid: 0000-0001-5317-4934

According to our database1, Raphael Martins Brum authored at least 12 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A Predictive Approach for Conditional Execution of Memristive Material Implication Stateful Logic Operations.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

2021
A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

2019
Evaluating the Impact of Accuracy Relaxation in the Reliability of GPU Register Files.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2018
Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library.
J. Electron. Test., 2018

2016
MagPDK: An open-source process design kit for circuit design with magnetic tunnel junctions.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

2015
Impact of dynamic voltage scaling and thermal factors on SRAM reliability.
Microelectron. Reliab., 2015

Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Potential applications based on NVM emerging technologies.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013
Evaluation of hybrid MRAM/CMOS cells for reconfigurable computing.
Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Trends on the application of emerging nonvolatile memory to processors and programmable devices.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2011
Embedded MRAM for high-speed computing.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

High Performance SoC Design Using Magnetic Logic and Memory.
Proceedings of the VLSI-SoC: Advanced Research for Systems on Chip, 2011


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