Rao Desineni

According to our database1, Rao Desineni authored at least 11 papers between 2000 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2016
Pylon: Towards an integrated customizable volume diagnosis infrastructure.
Proceedings of the 2016 IEEE International Test Conference, 2016

2013
Deriving Feature Fail Rate from Silicon Volume Diagnostics Data.
IEEE Des. Test, 2013

2010
Hard to find, easy to find systematics; just find them.
Proceedings of the 2011 IEEE International Test Conference, 2010

2006
Defect Modeling Using Fault Tuples.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior.
Proceedings of the 2006 IEEE International Test Conference, 2006

Extraction of defect density and size distributions from wafer sort test results.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Multiple-detect ATPG based on physical neighborhoods.
Proceedings of the 43rd Design Automation Conference, 2006

2005
Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

2004
Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2002
Fault Tuples in Diagnosis of Deep-Submicron Circuits.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2000
Universal test generation using fault tuples.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000


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