Randy Mooney

According to our database¹, Randy Mooney authored at least 19 papers between 1995 and 2014.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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On csauthors.net:

Bibliography

2014

A 4-32 Gb/s Bidirectional Link With 3-Tap FFE/6-Tap DFE and Collaborative CDR in 22 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2014

26.2 A 205mW 32Gb/s 3-Tap FFE/6-tap DFE bidirectional serial link in 22nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013

A Scalable 0.128-1 Tb/s, 0.8-2.6 pJ/bit, 64-Lane Parallel I/O in 32-nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2013

A scalable 0.128-to-1Tb/s 0.8-to-2.6pJ/b 64-lane parallel I/O in 32nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2010

A 47 , ˟, 10 Gb/s 1.4 mW/Gb/s Parallel Interface in 45 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2010

A 47×10Gb/s 1.4mW/(Gb/s) parallel interface in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009

Strong Injection Locking in Low- Q LC Oscillators: Modeling and Application in a Forwarded-Clock I/O Receiver.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

2008

A Scalable 5-15 Gbps, 14-75 mW Low-Power I/O Transceiver in 65 nm CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A 27Gb/s Forwarded-Clock I/O Receiver Using an Injection-Locked LC-DCO in 45nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Session 10 - Panel discussion Sure, Moore's Law can continue, but should it.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

Strong injection locking of low-Q LC oscillators.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2006

A 20Gb/s Embedded Clock Transceiver in 90nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

8-Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation, and clock de-skew.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2005

2004

Jitter in high-speed serial and parallel links.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Analysis of PLL clock jitter in high-speed serial links.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2003

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2003

1995

A 900 Mb/s bidirectional signaling scheme.

[BibT_eX]

[DOI]

Randy Mooney

Charles Dike

Shekhar Borkar

IEEE J. Solid State Circuits, December, 1995

Randy Mooney

Timeline

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Links

On csauthors.net:

Bibliography

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